FS6500-FS4500：NXP半导体数据手册——高效汽车级智能电源芯片

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NXP Semiconductors Data sheet:FS6500-FS4500 是一份详细的规格和技术文档，介绍了一款专为汽车行业设计的新型智能MOS器件——FS6500和FS4500。这款产品集成了多个输出功能，包括高性能的CAN Flexible Data (CAN FD) 和 LIN (Local Interconnect Network) 通信接口，旨在满足汽车电子系统对高效、可靠和安全的需求。该芯片的主要特点包括： 1. 多功能：作为一款电源管理集成电路，它提供了多种开关模式和线性电压调节器，包括低功耗模式（仅32微安），支持灵活的唤醒功能，适应不同的应用需求。 2. 高效性：内置先进的电源管理系统，确保在宽范围输入电压（低至2.7伏）和输出电流（高达2.2安培）下保持高效率。这有助于延长电池寿命并降低能耗。 3. 安全特性：FS6500/FS4500 设计了可配置的安全行为，包括Fail-safe 和 Fail-silent 模式，能够无缝融入安全性高的系统分区，实现ASIL-D级别的高完整性安全性能。 4. 标准兼容性：内置的CAN FD 接口符合 ISO 11898-2 和 -5 标准，确保与现有的CAN网络通信的兼容性。而 LIN 接口则满足 LIN 协议，为低速率数据交换提供可靠的连接。 5. 适用于汽车行业应用：这款芯片专为汽车市场设计，满足严苛的环境和电磁兼容性要求，适合用于各种汽车电子系统，如舒适性、娱乐、安全控制等模块。 NXP Semiconductors 的 FS6500-FS4500 是一款集成了CAN FD 和 LIN 接口的高性能、安全且低功耗的电源管理解决方案，为汽车行业提供了一个集成度高、可靠性强的选择，是现代汽车电子系统中不可或缺的组件。随着汽车电子设备的复杂性和自动化程度不断提高，这款芯片的广泛应用将推动汽车行业的创新和进步。

16 NXP Semiconductors

FS6500/FS4500

CAN_5V voltage regulator (continued)

LOR

VCAN

CAN

transient load regulation

•I

CAN_OUT

= 0 mA to 50 mA

–100–mV

(17)

VKAM voltage regulator

KAM

output voltage 3.0 3.5 4.0 V

KAM_OUT

KAM

output current – – 3.0 mA

KAM_LIM

KAM

output current limitation 4.0 – 10.0 mA

SUP_KAM

KAM

current consumption from V

SUP3

•I

KAM_OUT

= 0 mA

•I

KAM_OUT

< 1.0 mA

• 1.0 mA < I

KAM_OUT

< 3.0 mA

–

150

2.15

µA

Long duration timer

LDT

Timer current consumption (from V

SUP3

)–5.010µA

Fail-safe machine voltage supervisor

PRE_OV

PRE

overvoltage detection threshold 7.2 – 8.0 V

PRE_OV_HYST

PRE

overvoltage hysteresis – 0.1 – V

(17)

CORE_FB_UV

CORE

FB undervoltage detection threshold 0.67 – 0.773 V

CORE_FB_UV_D

CORE

FB undervoltage detection threshold - degraded mode 0.45 – 0.58 V

CORE_FB_UV_

HYST

CORE

FB undervoltage hysteresis 10 – 27 mV

(17)

CORE_FB_OV

CORE

FB overvoltage detection threshold 0.84 – 0.905 V

CORE_FB_OV_

HYST

CORE

FB overvoltage hysteresis 10 – 30 mV

(17)

CORE_FB_DRIFT

CORE_FB

drift versus FCRBM 50 100 150 mV

CCA_UV_5

CCA

undervoltage detection threshold (5.0 V config) 4.5 – 4.75 V

CCA_UV_5D

CCA

undervoltage detection threshold (degraded 5.0 V) 3.0 – 3.2 V

CCA_UV_33

CCA

undervoltage detection threshold (3.3 V config) 3.0 – 3.2 V

CCA_OV_5

CCA

overvoltage detection threshold (5.0 V config) 5.25 – 5.6 V

CCA_OV_33

CCA

overvoltage detection threshold (3.3 V config) 3.4 – 3.7 V

CCA_5_HYST

CCA

undervoltage and overvoltage hysteresis (5.0 V config) – 0.105 – V

(17)

CCA_33_HYST

CCA

undervoltage and overvoltage hysteresis (3.3 V config) – 0.07 – V

(17)

AUX_UV_5

AUX

undervoltage detection threshold (5.0 V config) 4.5 – 4.75 V

AUX_UV_5D

AUX

undervoltage detection threshold (degraded 5.0 V) 3.0 – 3.2 V

AUX_UV_33

AUX

undervoltage detection threshold (3.3 V config) 3.0 – 3.2 V

AUX_OV_5

AUX

overvoltage detection threshold (5.0 V config) 5.25 – 5.6 V

AUX_OV_33

AUX

overvoltage detection threshold (3.3 V config) 3.4 – 3.7 V

AUX_5_HYST

AUX

undervoltage and overvoltage hysteresis (5.0 V config) – 0.105 – V

(17)

AUX_33_HYST

AUX

undervoltage and overvoltage hysteresis (3.3 V config) – 0.07 – V

(17)

Notes

17. Guaranteed by design.

Table 5. Static electrical characteristics (continued)

= –40 °C to 125 °C, unless otherwise specified. V

SUP

= V

SUP_UV_L

to 36 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V

SUP

< 36 V, thermal dissipation must be considered (see Figure 32).

Symbol Parameter Min. Typ. Max. Unit Notes

NXP Semiconductors 17

FS6500/FS4500

Fail-safe outputs

RSTB_OL

Reset low output level (I_RSTB = 2.0 mA) – – 0.5 V

RSTB_LIM

Reset output current limitation 12 – 25 mA

RSTB_IL

Reset low level detection threshold (falling) 1.0 – – V

RSTB_IH

Reset high level detection threshold (rising) – – 2.0 V

RSTB_HYST

Reset hysteresis 200 – – mV

RSTB

PULL-DOWN

RSTB pull-down resistor – 1.0 – MΩ

FS0B_OL

FS0B low output level (I_FS0B = 2.0 mA) – – 0.5 V

FS0B_LIM

FS0B output current limitation 4.0 – 16 mA

FS0B_IL

FS0B low level detection threshold (falling) 1.0 – – V

FS0B_IH

FS0B high level detection threshold (rising) – – 2.0 V

FS0B_HYST

FS0B hysteresis 100 – – mV

FS0B

PULL-DOWN

FS0B pull-down resistor – 4.0 – MΩ

FS1B_OL

FS1B low output level (I_FS1B = 2.0 mA) – – 0.5 V

FS1B_LIM

FS1B output current limitation 4.0 – 16 mA

FS1B_IL

FS1B low level detection threshold (falling) 1.0 – – V

FS1B_IH

FS1B high level detection threshold (rising) – – 2.0 V

FS1B_HYST

FS1B hysteresis 100 – – mV

FS1B

PULL-DOWN

FS1B pull-down resistor – 4.0 – MΩ

Fail-safe pull-up

VPU_FS

VPU_FS circuitry consumption – 5.0 10 µA

VPU_FS_TH

VPU_FS falling threshold to assert FS1B (FS1B_trig) 2.9 3.2 3.5 V

VPU_FS

Resistor between VPRE and VPU_FS – 1.0 1.5 kΩ

(18)

Digital input

IO_IH

Digital high input voltage level (IO_0, IO_4, IO_5) 2.6 – – V

IO23_IH

Digital high input voltage level (IO_2, IO_3) 2.0 – – V

IO_IL

Digital low input voltage level (IO_0, IO_4, IO_5) – – 2.1 V

IO_HYST

Input voltage hysteresis (IO_0, IO_4, IO_5) 50 120 500 mV

(18)

IO23_IL

Digital low input voltage level (IO_2, IO_3) – – 0.9 V

IO23_HYST

Input voltage hysteresis (IO_2, IO_3) 200 450 700 mV

(18)

IO_IN_2:4

Input current for IO_2, IO_3 and IO_4 –5.0 – 5.0 µA

IO_IN_LPOFF

Input current for IO_0:5 in LPOFF –1.0 – 1.0 µA

Notes

18. Guaranteed by design

Table 5. Static electrical characteristics (continued)

= –40 °C to 125 °C, unless otherwise specified. V

SUP

= V

SUP_UV_L

to 36 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V

SUP

< 36 V, thermal dissipation must be considered (see Figure 32).

Symbol Parameter Min. Typ. Max. Unit Notes

18 NXP Semiconductors

FS6500/FS4500

Analog input - multi-purpose IOs

IO_ANA_WD

Measurable input voltage (wide range) 3.0 – 19 V

IO_ANA_TG

Measurable input voltage (tight range) 3.0 – 9.0 V

IO_IN_ANA

Input current for IO_0 and IO_5 –5.0 – 100 µA

(19)

Output gate driver (IO_4)

IO4_OH

High output level at I

IO4_OUT

= –2.0 mA V

PRE

– 1.5 – V

PRE

IO4_OL

Low output level at I

IO4_OUT

= +2.0 mA 0.0 – 1.0 V

IO4_OUT_SK

IO4_OUT_SC

Output current capability

2.0

–

–2.0

Analog multiplexer

AMUX_ACC

Voltage sense accuracy (V

SNS

, IO_0, IO_5) using 5.1 kΩ resistor –5.0 – 5.0 %

(20)

AMUX_WD_5

Divider ratio (wide input voltage range) at V

DDIO

= 5.0 V – 5.0 –

(21)

AMUX_WD_3P3

Divider ratio (wide input voltage range) at V

DDIO

= 3.3 V – 7.0 –

(21)

AMUX_TG_5

Divider ratio (tight input voltage range) at V

DDIO

= 5.0 V – 2.0 –

AMUX_TG_3P3

Divider ratio (tight input voltage range) at V

DDIO

= 3.3 V – 3.0 –

AMUX_REF1

Internal voltage Reference with 6.0 V < V

SUP

< 19 V 2.475 2.5 2.525 V

AMUX_REF2

Internal voltage reference with V

SUP

≤ 6.0 V or V

SUP

≥ 19 V 2.468 2.5 2.532 V

AMUX_TP_CO

Internal temperature sensor coefficient – 9.9 – mV/°C

(22)

AMUX_TP

Temperature sensor MUX_OUT output voltage (at T

= 165 °C) 2.08 2.15 2.22 V

Interrupt

INTB_OL

Low output level (I

INT

= 2.5 mA) – – 0.5 V

PU_INT

Internal pull-up resistor (connected to VDDIO) – 10 – KΩ

INT_LK

Input leakage current – – 1.0 µA

Digital interface

MISO

High output level on MISO (I

MISO

= 1.5 mA) V

DDIO

– 0.4 – – V

MISO

Low output level on MISO (I

MISO

= 2.0 mA) – – 0.4 V

MISO

Tri-state leakage current (V

DDIO

= 5.0 V) –5.0 – 5.0 µA

DDIO

Supply voltage for MISO output buffer 3.0 – 5.5 V

DDIO

Current consumption on VDDIO – 1.0 3.0 mA

SPI

SCLK, NCS, MOSI input current –1.0 – 1.0 µA

SPI_IH

SCLK, NCS, MOSI high input threshold 2.0 – – V

SPI_IL

SCLK, NCS, MOSI low input threshold – – 0.8 V

SPI

NCS, MOSI internal pull-up (pull-up to VDDIO) 200 400 800 KΩ

Notes

19. Valid for V

SUP3

≥ IO_5

20. If a higher resistor value than recommended is used, the accuracy degrades.

21. Wide range accuracy for input voltage from 9.0 V to 19 V

22. Guaranteed by design

Table 5. Static electrical characteristics (continued)

= –40 °C to 125 °C, unless otherwise specified. V

SUP

= V

SUP_UV_L

to 36 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V

SUP

< 36 V, thermal dissipation must be considered (see Figure 32).

Symbol Parameter Min. Typ. Max. Unit Notes

NXP Semiconductors 19

FS6500/FS4500

Debug

DEBUG_IL

Low input voltage threshold 2.1 2.35 2.8 V

DEBUG_IH

High input voltage threshold 4.35 4.6 4.97 V

DEBUG_LK

Input leakage current –10 – 10 µA

CAN transceiver (FD 2.0 Mbit/s)

CAN logic input pin (TXD)

TXD_IH

TXD high input threshold 0.7 x V

DDIO

– –V

TXD_IL

TXD low input threshold – – 0.3 x V

DDIO

TXD

PULL-UP

TXD main device pull-up 20 33 50 KΩ

TXD

TXD input leakage current, V

TXD

= V

DDIO

–1.0 – 1.0 µA

CAN logic output pin (RXD)

RXD_OL1

Low level output voltage (I

RXD

= 250 µA) – – 0.4 V

RXD_OL2

Low level output voltage (I

RXD

= 1.5 mA) – – 0.9 V

VOUT

HIGH

High level output voltage (I

RXD

= –250 µA, V

DDIO

= 3.0 V to 5.5 V) V

DDIO

– 0.4 – – V

CAN output pins (CANH, CANL)

DIFF_COM_MODE

Differential input comparator common mode range in normal mode –20 – 20 V

IN_DIFF

Differential input voltage threshold in normal mode 0.5 – 0.9 V

DIFF_COM_SLEEP

Differential input comparator common mode range in sleep mode –12 – 12 V

IN_DIFF_SLEEP

Differential input voltage threshold in sleep mode 0.4 – 1.1 V

IN_HYST

Differential input hysteresis (in TX, RX mode) 50 – – mV

IN_CHCL

CANH, CANL input resistance 5.0 – 50 kΩ

IN_DIFF

CAN differential input resistance 10 – 100 kΩ

INSLEEP

CANH, CANL input resistance device supplied and in CAN sleep mode 5.0 – 50 kΩ

IN_MATCH

Input resistance matching –3.0 – 3.0 %

CANH

CANH output voltage (45 Ω < R

BUS

< 65 Ω)

• TX dominant state

• TX recessive state

2.75

2.0

–

2.5

4.5

3.0

CANL

CANL output voltage (45 Ω < R

BUS

< 65 Ω)

• TX dominant state

• TX recessive state

0.5

2.0

–

2.5

2.25

3.0

CAN_SYM

CAN dominant voltage symmetry (V

CANL

+ V

CANH

) 4.5 5.0 5.5 V

-V

Differential output voltage

• TX dominant state (45 Ω < R

BUS

< 65 Ω)

• TX recessive state

1.5

–50

2.0

0.0

3.0

CANL-SK

CANL sink current under short-circuit condition (V

CANL

≤ 12 V, CANL

driver ON, TXD low)

40 – 100 mA

CANH-SC

CANH source current under short-circuit condition (V

CANH

= –2.0 V,

CANH driver ON, TXD low)

–100 – –40 mA

CANLP

CANL, CANH output voltage in sleep modes. No termination load. –0.1 0.0 0.1 V

Table 5. Static electrical characteristics (continued)

= –40 °C to 125 °C, unless otherwise specified. V

SUP

= V

SUP_UV_L

to 36 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V

SUP

< 36 V, thermal dissipation must be considered (see Figure 32).

Symbol Parameter Min. Typ. Max. Unit Notes

20 NXP Semiconductors

FS6500/FS4500

CAN output pins (continued)

CAN

CANH, CANL input current, device unsupplied, (V

CANH,

CANL

= 5.0 V)

•V

SUP

and V

CAN

connected to GND

•V

SUP

and V

CAN

connected to GND via 47 kΩ resistor

–10

–

µA

(23)

Overtemperature detection 160 – – °C

HYST

Overtemperature hysteresis – – 20 °C

LIN transceiver (when 7.0 V < V

SUP

1,2,3 < 18 V, unless otherwise specified)

LIN logic input pin (TXDL)

TXDL_IH

TXDL high input threshold 2.0 – – V

TXDL_IL

TXDL low input threshold – – 0.8 V

TXDL

PULL-UP

TXDL internal pull-up (to VDDIO) 20 33 50 kΩ

TXDL

TXD input leakage current, V

TXDL

= VDDIO –1.0 – 1.0 µA

LIN logic input pin (RXDL)

RXDL_OL1

Low level output voltage (I

RXDL

= 250 µA) – – 0.4 V

RXDL_OL2

Low level output voltage (I

RXDL

= 1.5 mA) – – 0.9 V

RXDL_OUT_HIGH

High level output voltage (I

RXDL

= –250 µA, V

DDIO

= 3.0 V to 5.5 V) V

DDIO

– 0.4 – – V

LIN output pin

BUS_PAS_DOM

Input leakage current at the receiver. dominant state (Driver OFF,

BAT

= 12 V, V

BUS

= 0 V)

–1.0 – – mA

(24)

BUS_PAS_REC

Input leakage current at the receiver. recessive state (Driver OFF,

8.0 V < V

BAT

< 18 V, 8.0 V < V

BUS

< 18 V, V

BUS

≥ V

BAT

)

––20µA

DRIVER_DOM

Driver dominant voltage – – 0.251 V

SUP

BUS_DOM

Receiver dominant state – – 0.4 V

SUP

BUS_REC

Receiver recessive state 0.6 V

SUP

––V

BUS_WU

LIN wake-up detection threshold (7.0 V< V

SUP

< 18 V) 0.4 V

SUP

– 0.6 V

SUP

LIN_UV

SUP

undervoltage threshold – – 7.0 V

SER_DIODE

Series diode voltage drop (D

SER_MASTER

and D

SER_INT

in pull-up path) 0.4 0.7 1.0 V

BUS_LIM

Current limitation for driver dominant state (V

BUS

= 18 V) 40 – 200 mA

(25)

SLAVE

LIN pull-up resistor 20 – 60 kΩ

SHIFT_GND

Ground shift (V

SHIFT_GND

= V

GND_ECU

– V

GND_BATTERY)

0.0 – 11.5%V

BAT

SHIFT_BAT

Battery voltage shift (V

SHIFT_BAT

= V

BATTERY

– V

SHIFT_GND

– V

BAT

) 0.0 – 11.5%V

BAT

(26)

SHIFT_DIF

Difference between battery shift and ground shift

SHIFT_DIF

= V

SHIFT_BAT

– V

SHIFT_GND

)

0.0 – 8.0% V

BAT

(27)

Notes

23. Guaranteed by design and characterization

24. V

BAT

is the voltage at the input of the control unit.

25. Current flowing inside the pin. A transceiver must be capable to sink at least 40 mA.

26. V

BAT

: voltage across the battery connectors of the vehicle. V

GND_ECU

: voltage on the local ECU ground connector with respect to battery ground

of the vehicle (V

GND_BATTERY

27. This constraint refers to duty cycle D1 and D2 only.

Table 5. Static electrical characteristics (continued)

= –40 °C to 125 °C, unless otherwise specified. V

SUP

= V

SUP_UV_L

to 36 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V

SUP

< 36 V, thermal dissipation must be considered (see Figure 32).

Symbol Parameter Min. Typ. Max. Unit Notes

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