NXP LPC54616微控制器用户手册

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"LPC54616手册.pdf - LPC54616寄存器手册，由NXP官网提供，包含LPC54616微控制器的相关信息，包括ARM Cortex-M4、32位处理器、LCD、Ethernet AVB等特性。" LPC54616是一款由NXP半导体公司推出的微控制器，基于ARM Cortex-M4内核，适用于多种应用场合。该手册是UM10912用户手册的第2.4版，发布于2019年11月11日，包含了自2019年10月11日以来的最新更新，如5.6.8节关于ISP参数数组的新内容。 LPC54616微控制器拥有丰富的功能集，包括但不限于以下特性： 1. **ARM Cortex-M4**：这款高性能、低功耗的处理器核心支持浮点运算，适合处理复杂的计算任务。 2. **32位微控制器**：提供高效的数据处理能力，适应现代嵌入式系统的需求。 3. **LCD控制器**：内置LCD控制器，可支持图形和文本显示，适用于各种人机交互界面。 4. **Ethernet AVB**（Audio/Video Bridging）：支持高带宽音频和视频传输，适用于多媒体应用。 5. **SPIFI**（Serial Peripheral Interface Flash Interface）：快速闪存接口，提高程序加载速度。 6. **SCT/PWM**（State Configurable Timer/Pulse Width Modulation）：灵活的定时器和脉宽调制模块，可用于电机控制和其他定时任务。 7. **USB Host和USB Device**：支持USB主机和设备模式，便于与其他USB设备连接。 8. **CAN FD**（Controller Area Network with Flexible Data-Rate）：高速CAN总线，用于汽车和工业自动化通信。 9. **I2C**和**I2S**：标准的串行通信接口，用于传感器和音频设备。 10. **EEPROM模拟**：内置模拟EEPROM功能，无需额外硬件存储非易失性数据。 11. **Flash和EMC**（Embedded Memory Controller）：控制内部和外部的闪存以及增强型内存控制器。 12. **SDRAM控制器**：支持SDRAM，提供更快的数据访问速度。 13. **DMIC**（Digital Microphone Interface）：数字麦克风接口，用于高质量音频输入。 14. **SDIO接口和SD卡接口**：用于连接SD或SDIO存储卡，扩展存储容量。 15. **LCD控制器**：用于驱动液晶显示屏，提供多种显示选项。 16. **eCRP**（Enhanced Code Read Protection）：增强的代码保护功能，防止非法读取和修改程序代码。 17. **SHA**（Secure Hash Algorithm）：安全哈希算法，用于加密和验证数据完整性。该手册还涉及了LPC54616的配置、初始化、外设操作、调试工具使用以及ISP（In-System Programming）等主题。例如，5.5.5节更新了5.5.1至5.5.4的内容，5.4.5.15节添加了关于ISP读取唯一ID的信息，5.6.8节更新了指向ISP参数数组的描述。这些更新确保开发者能够利用最新的功能和改进进行有效的开发工作。 LPC54616手册是针对这款微控制器的重要参考资料，对于理解和使用LPC54616的开发者来说，它是编程必备的文档，涵盖了从基本概念到高级特性的全面介绍。通过深入学习该手册，开发者可以充分利用LPC54616的潜能，设计出高效、可靠的嵌入式系统。

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User manual Rev. 2.4 — 11 November 2019 16 of 1149

NXP Semiconductors

UM10912

Chapter 1: LPC546xx Introductory information

1.9.1 Ordering options

Table 2. Ordering options

Type number

Package Name

Frequency/MHz

Flash/kB

SRAM/kB

FS USB

HS USB

Ethernet AVB

Classic CAN

CAN FD

LCD

Flexcomm

Interface

EMC data bus

width (bit)

GPIO

SHA

LPC54628 devices (HS/FS USB, Ethernet, CAN FD, CAN 2.0, LCD, SHA)

LPC54628J512ET180 TFBGA180 220 512 200 yes yes yes yes yes yes 10 8/16 145 yes

LPC54618 devices (HS/FS USB, Ethernet, CAN FD, CAN 2.0, LCD)

LPC54618J512ET180 TFBGA180 180 512 200 yes yes yes yes yes yes 10 8/16 145 no

LPC54618J512BD208 LQFP208 180 512 200 yes yes yes yes yes yes 10 8/16/32 171 no

LPC54616 devices (HS/FS USB, Ethernet, CAN FD, CAN 2.0)

LPC54616J256ET180 TFBGA180 180 256 136 yes yes yes yes yes no 10 8/16 145 no

LPC54616J512BD208 LQFP208 180 512 200 yes yes yes yes yes no 10 8/16/32 171 no

LPC54616J512ET100 TFBGA100 180 512 200 yes yes yes yes yes no 9 8/16 64 no

LPC54616J512BD100 LQFP100 180 512 200 yes yes yes yes yes no 9 8/16 64 no

LPC54608 devices (HS/FS USB, Ethernet, CAN 2.0, LCD)

LPC54608J512ET180 TFBGA180 180 512 200 yes yes yes yes no yes 10 8/16 145 no

LPC54608J512BD208 LQFP208 180 512 200 yes yes yes yes no yes 10 8/16/32 171 no

LPC54607 devices (HS/FS USB, LCD)

LPC54607J256ET180 TFBGA180 180 256 136 yes yes no no no yes 10 8/16 145 no

LPC54607J512ET180 TFBGA180 180 512 200 yes yes no no no yes 10 8/16 145 no

LPC54607J256BD208 LQFP208 180 256 136 yes yes no no no yes 10 8/16/32 171 no

LPC54606 devices (HS/FS USB, Ethernet, CAN 2.0)

LPC54606J256ET180 TFBGA180 180 256 136 yes yes yes yes no no 10 8/16 145 no

LPC54606J512BD208 LQFP208 180 512 200 yes yes yes yes no no 10 8/16/32 171 no

LPC54606J256ET100 TFBGA100 180 256 136 yes yes yes yes no no 9 8/16 64 no

LPC54606J512ET100 TFBGA100 180 512 200 yes yes yes yes no no 9 8/16 64 no

LPC54606J256BD100 LQFP100 180 256 136 yes yes yes yes no no 9 8/16 64 no

LPC54606J512BD100 LQFP100 180 512 200 yes yes yes yes no no 9 8/16 64 no

LPC54605 devices (HS/FS USB)

LPC54605J256ET180 TFBGA180 180 256 136 yes yes no no no no 10 8/16 145 no

LPC54605J512ET180 TFBGA180 180 512 200 yes yes no no no no 10 8/16 145 no

LPC54605J256BD100 LQFP100 180 256 136 yes yes no no no no 9 8/16 64 no

LPC54605J512BD100 LQFP100 180 512 200 yes yes no no no no 9 8/16 64 no

LPC54605J256ET100 TFBGA100 180 256 136 yes yes no no no no 9 8/16 64 no

LPC54605J512ET100 TFBGA100 180 512 200 yes yes no no no no 9 8/16 64 no

User manual Rev. 2.4 — 11 November 2019 17 of 1149

2.1 General description

The LPC546xx incorporates several distinct memory regions. Figure 2 shows the overall

map of the entire address space from the user program viewpoint following reset.

The APB peripheral area (detailed in Figure 3

) is divided into fixed 4 KB slots to simplify

addressing.

The registers incorporated into the CPU, such as NVIC, SysTick, and sleep mode control,

are located on the private peripheral bus.

2.1.1 Memory map and peripheral addressing

The ARM Cortex-M4 processor has a single 4 GB address space. The following table

shows how this space is used on the LPC546xx.

UM10912

Chapter 2: LPC546xx Memory map

Rev. 2.4 — 11 November 2019 User manual

Table 3. Memory usage and details

Address range General Use Address range details and description

0x0000 0000 to 0x1FFF FFFF On-chip

non-volatile

memory

0x0000 0000 - 0x0007 FFFF Flash memory (512 KB).

Boot ROM 0x0300 0000 - 0x0300 FFFF Boot ROM with flash services in a 64 KB

space.

SRAMX 0x0400 0000 - 0x0400 7FFF I&D SRAM bank (32 KB).

SPI Flash

Interface (SPIFI)

0x1000 0000 - 0x17FF FFFF SPIFI memory mapped access space

(128 MB).

0x2000 0000 to 0x3FFF FFFF SRAM Banks 0x2000 0000 - 0x2002 7FFF SRAM banks (160 KB).

SRAM bit band

alias addressing

0x2200 0000 - 0x23FF FFFF SRAM bit band alias addressing (32 MB)

0x4000 0000 to 0x7FFF FFFF APB peripherals 0x4000 0000 - 0x4001 FFFF APB slave group 0 up to 32 peripheral

blocks of 4 KB each (128 KB).

0x4002 0000 - 0x4003 FFFF APB slave group 1 up to 32 peripheral

blocks of 4 KB each (128 KB).

0x4004 0000 - 0x4005 FFFF APB asynchronous slave group 2 up to

32 peripheral blocks of 4 KB each

(128 KB).

AHB peripherals 0x4008 0000 - 0x400B FFFF AHB peripherals (256 KB).

USB SRAM 0x4010 0000 - 0x4010 1FFC USB SRAM (8 KB)

Peripheral bit

band alias

addressing

0x4200 0000 - 0x43FF FFFF Peripheral bit band alias addressing

(32 MB)

User manual Rev. 2.4 — 11 November 2019 18 of 1149

NXP Semiconductors

UM10912

Chapter 2: LPC546xx Memory map

[1] Can be up to 256 MB, upper address 0x8FFF FFFF, if the address shift mode is enabled. See

EMCSYSCTRL register bit 0 (Section 7.5.71

[2] Can be up to 128 MB, upper address 0x97FF FFFF, if the address shift mode is enabled. See

EMCSYSCTRL register bit 0 (Section 7.5.71

2.1.2 SRAM

The Main SRAM is comprised of up to a total 160 KB of contiguous, on-chip static RAM

memory (this is in addition to SRAMX as noted in the next section below, so the total

device SRAM can be up to 200 KB). The Main SRAM is further divided to allow for more

control of power usage when less SRAM is required: SRAM0 (up to 64 KB), SRAM1 (up to

32 KB), SRAM2 (up to 32 KB), and SRAM3 (up to 32 KB). Each SRAM has a separate

clock control and power switch, see Section 7.5.19 “

AHB Clock Control register 0” and

Section 7.5.84 “

Power Configuration register 0”.

An additional on-chip static RAM memory is available that is not contiguous to the main

SRAM. This RAM is called SRAMX, and resides on the local buses (I-Code and D-Code)

of the Cortex-M4, and on the main bus of the Cortex-M0+. This RAM can be used, for

example, as the location for the program stack, common data, or any other use where a

separate access away from the Main SRAM has an advantage. SRAMX can be disabled

or enabled in the SYSCON block to save power. See Section 7.5.84 “

Power Configuration

used as a general purpose SRAM when not used for USB.

0x8000 0000 to 0xDFFF FFFF Off-chip Memory

via the External

Memory

Controller

Four static memory chip selects:

0x8000 0000 - 0x83FF FFFF Static memory chip select 0 (up to 64

MB)

[1]

0x8800 0000 - 0x8BFF FFFF Static memory chip select 1 (up to 64

MB)

[2]

0x9000 0000 – 0x93FF FFFF Static memory chip select 2 (up to 64

MB)

0x9800 0000 - 0x9BFF FFFF Static memory chip select 3 (up to 64

MB)

Four dynamic memory chip selects:

0xA000 0000 - 0xA7FF FFFF Dynamic memory chip select 0 (up to

256MB)

0xA800 0000 - 0xAFFF FFFF Dynamic memory chip select 1 (up to

256MB)

0xB000 0000 - 0xB7FF FFFF Dynamic memory chip select 2 (up to

256MB)

0xB800 0000 - 0xBFFF FFFF Dynamic memory chip select 3 (up to

256MB)

0xE000 0000 to 0xE00F FFFF Cortex-M4

Private

Peripheral Bus

0xE000 0000 - 0xE00F FFFF Cortex-M4 related functions, includes

the NVIC and System Tick Timer.

Table 3. Memory usage and details

Address range General Use Address range details and description

User manual Rev. 2.4 — 11 November 2019 19 of 1149

NXP Semiconductors

UM10912

Chapter 2: LPC546xx Memory map

2.1.2.1 SRAM usage notes

Although always contiguous on all LPC546xx devices, SRAM0, SRAM1, SRAM2, and

SRAM3 are placed on different AHB matrix ports. This allows user programs to potentially

obtain better performance by dividing RAM usage among the ports. For example,

simultaneous access to SRAM0 by the CPU and SRAM1 by the system DMA controller

does not result in any bus stalls for either master.

Generally, data being communicated via peripherals will be accessed by the CPU at some

point, even when peripheral data is mainly being transferred via DMA. So, in order to

minimizing data read/write stalls, data buffers may be placed in RAMs on different AHB

matrix ports. For instance, if DMA is writing to one buffer on a specific AHB matrix port

while the CPU is reading data from a buffer on a different AHB matrix port, there is no stall

for either the CPU or the DMA. Sequences of data from the same peripheral could be

alternated between RAM on each port. This could be helpful if DMA fills or empties a RAM

buffer, then signals the CPU before proceeding on to a second buffer. The CPU would

then tend to access the data while the DMA is using the other RAM.

2.1.2.2 Bit-band addressing

The ARM Cortex-M4 CPU provides a bit-band addressing feature. This offers efficient bit

accesses to selected memory regions.

Bits in the address region 0x2000 0000 to 0x200F FFFF (bits addressed at addresses

0x2200 0000 to 0x23FF FFFF) include the entire main SRAM area (does not include

SRAMX which is at a lower address).

Bits in the address region 0x4000 0000 to 0x400F FFFF (bits addressed at addresses

0x4200 0000 to 0x43FF FFFF) include all AHB and APB peripherals. This space does not

include the USB RAM and the EEPROM.

Reads from bit-band addresses return the respective bit from the bit-band region. Writes

perform an atomic read-modify-write on the respective bit of the bit-band region. For

details, see the ARM Cortex-M4 technical reference manual.

To calculate a bit band address:

Bit address = (Byte offset within bit-band space * 32) + (bit number in byte * 4) + bit-band

base address

Where:

• Bit addressable RAM base address = 0x2000 0000

• AHB/APB peripheral base address = 0x4000 0000

• RAM bit-band base address = 0x2200 0000

Table 4. SRAM configuration

SRAMX SRAM0 SRAM1 SRAM2 SRAM3 USB RAM

(total SRAM = up to 200 kB)

Size Up to 32 kB Up to 64 kB Up to 32 kB Up to 32 kB Up to 32 kB 8 kB

Address

range

Begins at 0x0400

0000

Begins at

0x2000 0000

Begins at

0x2001 0000

Begins at

0x2001 8000

Begins at

0x2002 0000

If present,

begins at

0x4010 0000

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