Xilinx 7Series 存储接口IP解决方案v4.1用户指南

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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 16

UG586 April 4, 2018 www.xilinx.com

10/19/2011 1.2

• MIS 1.3 release. Updated ISE Design Suite version to 13.3.

• Chapter 1: Added step 2 to MIS Output Options, page 26. Added note about optional

use of the memory controller to Controller Options, page 30. Added arbitration

scheme to AXI Parameter Options, page 33. Added description of DCI Cascade under

Figure 1-23. Updated text about devices with SSI technology and SLRs on page 41

and page 187. Changed error to tg_compare_error on page 42. Replaced Table 1-8.

Added qdr_wr_cmd_o, vio_fixed_instr_value, vio_fixed_bl_value, vio_pause_traffic,

and vio_data_mask_gen signals to Table 1-13. Added signals to the User Interface in

Figure 1-49 and Figure 1-51. Added app_sr_req, app_sr_active, app_ref_req,

app_ref_ack, app_zq_req, and app_zq_ack signals to Table 1-17. Added app_wdf_rdy,

app_ref_req, app_ref_ack, app_zq_req, app_zq_ack, Read Priority with Starve Limit

(RD_PRI_REG_STARVE_LIMIT), Native Interface Maintenance Command Signals, User

Refresh, and User ZQ sections. Added C_RD_WR_ARB_ALGORITHM to Table 1-19.

Updated fields in Table 1-84, changed Hi Index (Rank) to Rank Count, and added CAS

slot field. Updated AXI Addressing and Physical Layer Interface (Non-Memory

Controller Design). Added Figure 1-75 through Figure 1-77 in Write Path. In

Table 1-92, removed DISABLED option from RTT_NOM for DDR3_SDRAM, changed

RTT_NOM to RTT_WR in RTT_WR, updated SIM_BYPASS_INIT_CAL, and updated table

note 2. In Table 1-93, updated tZQI and added USER_REFRESH. Added Table 1-94. In

Configuration, updated constraints example and removed paragraph about SCL and

SDA.

• Chapter 2: Added step 2 to MIS Output Options, page 275. Added Input Clock Period

description in Controller Options, page 279. Added Debug Signals Control and

Internal Vref Selection options to FPGA Options, page 282. Added I/O Planning

Options, page 285. In System Pins Selection, page 288, changed cal_done signal to

init_calib_complete and error signal to tg_compare_error. Replaced Table 2-2.

Changed file names in Table 2-5. Updated signal names in Figure 2-38, Figure 2-39,

and Figure 2-40. Updated signal names in Table 2-7. Added CPT_CLK_CQ_ONLY and

updated value for SIM_BYPASS_INIT_CAL in Table 2-10. Added Table 2-11. Updated

pinout rules in Pinout Requirements, page 337. Added paragraph about DCI and

IN_TERM after Table 2-12. Added Debugging QDR II+ SRAM Designs, page 340.

• Chapter 3: Added step 2 to MIS Output Options, page 375. Added Input Clock Period

description in Controller Options. Added Debug Signals Control and Internal Vref

Selection options to FPGA Options, page 382. In System Pins Selection, changed

cal_done signal to init_calib_complete and error signal to tg_compare_error. Changed

file names in Table 3-6. Removed Table 3-12, which contained Reserved signals not

used. Added rst_phaser_ref to Table 3-11. Removed PHY-Only Interface section. In

Table 3-14, added RLD_ADDR_WIDTH, MEM_TYPE, CLKIN_PERIOD, and SIMULATION,

and renamed CLKFBOUT_MULT, CLKOUT0_DIVIDE, CLKOUT1_DIVIDE,

CLKOUT2_DIVIDE, and CLKOUT3_DIVIDE. Updated Table 3-15. Added paragraph

about DCI and IN_TERM after Table 3-24.

• Added Chapter 5, Multicontroller Design.

Date Version Revision

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UG586 April 4, 2018 www.xilinx.com

Table of Contents

Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Using MIG in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Synplify Pro Black Box Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Core Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Designing with the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Interfacing to the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Customizing the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Debugging DDR3/DDR2 Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Chapter 2: QDR II+ Memory Interface Solution

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Using MIG in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Core Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Customizing the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

Debugging QDR II+ SRAM Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

Using MIG in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

Core Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

Customizing the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

Debugging RLDRAM II and RLDRAM 3 Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

Chapter 4: LPDDR2 SDRAM Memory Interface Solution

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

Using MIG in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Core Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

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