KCPSM3微控制器手册：Picoblaze入门

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"KCPSM3 Manual使用手册 picoblaze入门教程" 本文档是关于KCPSM3微型控制器的使用手册，同时也包含了picoblaze的入门教程。KCPSM3是Xilinx公司设计的一种8位微控制器，适用于Spartan-3、Virtex-II和Virtex-II Pro系列的FPGA（现场可编程门阵列）。对于Spartan-II (E)和Virtex (E)，则推荐使用KCPSM的早期版本。KCPSM3还支持Virtex-II Pro系列，而KCPSM2则服务于Virtex-II和Virtex-II Pro平台。 KCPSM3的主要特点是其小巧的体积和高效的性能。在了解KCPSM3时，我们需要知道它的尺寸和性能表现。KCPSM3的架构由一系列功能集组成，包括常量(k)编码、VHDL的使用、程序ROM的连接、Verilog和System Generator的指令集等。 KCPSM3的指令集是其核心部分，包括但不限于： 1. ADDCY：带进位的加法操作 2. SUB：减法操作 3. SUBCY：带进位的减法操作 4. COMPARE：比较操作 5. SR0, SR1, SRX, SRA, RR：移位和旋转指令 6. SL0, SL1, SLX, SLA, RL：左移和右移指令 7. OUTPUT：输出指令 8. INPUT：输入指令 9. STORE：存储指令 10. FETCH：读取指令 11. READ and WRITE TO BE：读写接口信号 12. RESET：复位指令 13. CONSTANT Directive：常量指令 14. NAMEREG Directive：命名寄存器指令 15. ADDRESS Directive：地址指令文档还讨论了KCPSM3与KCPSM2之间的兼容性，以及与picoblaze的对比。picoblaze是一种简单的微控制器核，用于教育和原型设计。文档提供了中断处理的基本知识和工作示例，包括中断处理的基本原理、VHDL中的中断服务例程设计、中断操作的流程以及中断脉冲的定时。 KCPSM3的指令集和汇编器提示提供了优化代码和提高性能的建议。此外，手册中的JUMP、CALL、RETURN和RET指令是控制流程的关键，用于跳转、调用子程序、返回主程序和结束子程序。这份使用手册是学习和应用KCPSM3以及picoblaze微控制器的宝贵资源，涵盖了从基本概念到高级特性的全面内容，适合初学者和有经验的FPGA开发者参考使用。

Using KCPSM3 (VHDL)

The principle method by which KCPSM3 will be used is in a VHDL design flow. The KCPSM3 macro is provided as source VHDL

(kcspm3.vhd) which has been written to provide an optimum and predictable implementation in a Spartan-3 or Virtex-II(PRO)

device. The code is suitable for implementation and simulation of the macro. It has been developed and tested using XST for

implementation and ModelSim for simulation. The code should not be modified in any way.

component kcpsm3

Port ( address

instruction

port_id

write_strobe

out std_logic_vector(9 downto 0);

in std_logic_vector(17 downto 0);

out std_logic_vector(7 downto 0);

out std_logic;

VHDL Component

declaration of KCPSM3

out_port

read_strobe

in_port

interrupt

interrupt_ack

reset

clk

out std_logic_vector(7 downto 0);

out std_logic;

in std_logic_vector(7 downto 0);

in std_logic;

out std_logic;

in std_logic;

in std_logic);

end component;

processor: kcpsm3

port map( address

instruction

port_id

address_signal,

instruction_signal,

port_id_signal,

VHDL Component

instantiation of KCPSM3

write_strobe

out_port

read_strobe

in_port

interrupt

interrupt_ack

reset

clk

write_strobe_signal,

out_port_signal,

read_strobe_signal,

in_port_signal,

interrupt_signal,

interrupt_ack_signal,

reset_signal,

clk_signal);

KCPSM3 Manual 13

Verilog and System Generator

Although the primary design flow is VHDL, KCPSM3 can be used in any design flow supported by Xilinx. The assembler also

generates program memory definition files suitable for Verilog and the Simulink based System Generator design flows.

<filename>.v - The assembler generates a Verilog file in which a block RAM and its initial contents are defined (see assembler

notes for more detail). This Verilog can be used for implementation and simulation of the processor. The kcspm3.ngc file will be

used to define the processor.

kcpsm3.ngc - The NGC file provided was generated by synthesising the kcpsm3.vhd file with XST (without inserting I/O

buffers). This file can be used as a „black box‟ in a Spartan-3, Virtex-II or Virtex-IIPRO design, and it will be merged with the

rest of your design during the translate phase (ngdbuild). Note that busses are defined in the style „IN_PORT<7:0>‟ with

individual signals „in_port_0‟ through to „in_port_7‟.

<filename>.m - The assembler generates a m-function used to define the contents of a System Generator memory block within

the MATLAB Simulink environment. (see System Generator documentation for more information on this design flow).

<filename>.coe - The COE file generated by the assembler is suitable for use with the Xilinx Core Generator. The file defines

the initial contents of a block ROM. The files generated by Core Generator can then be used as normal in your chosen design

flow and connected to the kcpsm3 „black box‟ in your design (see assembler notes for more details).

Simulation Models

If the NGC file is used in the design flow, then some form of back annotated description will be required for simulation of your

design in order to fill in the „black box‟ details. The following command can be used to generate a Verilog simulation model (see

the Xilinx online manuals for more details - Synthesis and Simulation Design Guide - section 6).

ngd2ver kcspm3.ngd sim_model_kcpsm3.v

KCPSM3 Manual 15

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