ATmega328P：高性能低功耗微控制器

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"ATmega328P是一款高性能、低功耗的AVR 8位微控制器，常用于Arduino平台，提供了丰富的功能和内存资源。" ATmega328P是Atmel公司（现已被Microchip Technology收购）设计的一款广泛应用的微控制器，其核心基于高效的RISC（精简指令集计算）架构，具有以下特点： 1. 高性能：该芯片可在高达20MHz的时钟频率下工作，提供最高达20 MIPS（每秒百万指令）的处理能力。这使得ATmega328P能够快速执行任务，满足许多嵌入式系统的需求。 2. 低功耗：设计考虑了能源效率，适合电池供电或对功耗有严格要求的设备。它能在保持高性能的同时，实现低功耗运行。 3. 内存结构：ATmega328P提供了不同大小的非易失性存储器（NVM），包括4/8/16/32KB的闪存程序存储器、256/512/512/1KB的EEPROM和512/1K/1K/2KB的内部SRAM。这些内存部分都支持在系统编程（ISP），并且具备独立的锁定位，可以实现固件的安全保护。 4. 写/擦除周期和数据保留时间：闪存可承受至少10,000次写/擦除操作，而EEPROM则可以达到100,000次，数据在特定温度下可保留20年（85°C）至100年（25°C）。 5. 多样化的外设功能：包括两个8位定时器/计数器、一个16位定时器/计数器，以及带有独立预分频器、比较模式和捕捉模式的功能。此外，还有一个实时计数器和独立振荡器，以及六个PWM通道。对于需要模拟信号处理的应用，ATmega328P还配备了8通道10位ADC。 6. 在系统编程（ISP）和安全特性：芯片支持通过内部引导程序进行在系统编程，允许用户更新固件而不需从电路板上拆卸芯片。同时，它还提供了编程锁功能，以确保软件的安全性。 7. 封装形式：ATmega328P有多种封装选择，如TQFP、QFN/MLF，以适应不同的应用需求和空间限制。在Arduino世界中，ATmega328P通常是Arduino Uno等开发板的核心组件，其强大的处理能力和丰富的外设接口使得它成为初学者和专业开发者进行嵌入式系统开发的理想选择。无论是控制电机、读取传感器数据还是执行复杂的算法，ATmega328P都能够胜任。

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

7. AVR Memories

7.1 Overview

This section describes the different memories in the ATmega48PA/88PA/168PA/328P. The AVR

architecture has two main memory spaces, the Data Memory and the Program Memory space.

In addition, the ATmega48PA/88PA/168PA/328P features an EEPROM Memory for data stor-

age. All three memory spaces are linear and regular.

7.2 In-System Reprogrammable Flash Program Memory

The ATmega48PA/88PA/168PA/328P contains 4/8/16/32K bytes On-chip In-System Repro-

grammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits

wide, the Flash is organized as 2/4/8/16K x 16. For software security, the Flash Program mem-

ory space is divided into two sections, Boot Loader Section and Application Program Section in

ATmega88PA and ATmega168PA. See SELFPRGEN description in section ”SPMCSR – Store

Program Memory Control and Status Register” on page 292 for more details.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATmega48PA/88PA/168PA/328P Program Counter (PC) is 11/12/13/14 bits wide, thus address-

ing the 2/4/8/16K program memory locations. The operation of Boot Program section and

associated Boot Lock bits for software protection are described in detail in ”Self-Programming

the Flash, ATmega48PA” on page 269 and ”Boot Loader Support – Read-While-Write Self-Pro-

gramming, ATmega88PA, ATmega168PA and ATmega328P” on page 277. ”Memory

Programming” on page 294 contains a detailed description on Flash Programming in SPI- or

Parallel Programming mode.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Tim-

ing” on page 13.

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

7.3.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU

cycles as described in Figure 7-4.

Figure 7-4. On-chip Data SRAM Access Cycles

7.4 EEPROM Data Memory

The ATmega48PA/88PA/168PA/328P contains 256/512/512/1K bytes of data EEPROM mem-

ory. It is organized as a separate data space, in which single bytes can be read and written. The

EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the

EEPROM and the CPU is described in the following, specifying the EEPROM Address Regis-

ters, the EEPROM Data Register, and the EEPROM Control Register.

”Memory Programming” on page 294 contains a detailed description on EEPROM Programming

in SPI or Parallel Programming mode.

7.4.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 7-2. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code contains instruc-

tions that write the EEPROM, some precautions must be taken. In heavily filtered power

supplies, V

is likely to rise or fall slowly on power-up/down. This causes the device for some

period of time to run at a voltage lower than specified as minimum for the clock frequency used.

See ”Preventing EEPROM Corruption” on page 20 for details on how to avoid problems in these

situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

7.4.2 Preventing EEPROM Corruption

During periods of low V

CC,

the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low V

reset Protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the power supply voltage is sufficient.

7.5 I/O Memory

The I/O space definition of the ATmega48PA/88PA/168PA/328P is shown in ”Register Sum-

mary” on page 423.

All ATmega48PA/88PA/168PA/328P I/Os and peripherals are placed in the I/O space. All I/O

locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data

between the 32 general purpose working registers and the I/O space. I/O Registers within the

address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In

these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

Refer to the instruction set section for more details. When using the I/O specific commands IN

and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data

space using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega48PA/88PA/168PA/328P is a complex microcontroller with more peripheral units than

can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For

the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD

instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore

be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

7.5.1 General Purpose I/O Registers

The ATmega48PA/88PA/168PA/328P contains three General Purpose I/O Registers. These

registers can be used for storing any information, and they are particularly useful for storing

global variables and Status Flags. General Purpose I/O Registers within the address range 0x00

- 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

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