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Preface
is book targets engineers and researchers familiar with many basic computer architecture con-
cepts who are interested in learning about on-chip networks. is work is designed to be a short
synthesis of the most critical concepts in on-chip network design. We envision this book as a
resource for both understanding on-chip network basics and for providing an overview of state-
of-the-art research in on-chip networks. We believe that an overview that teaches both funda-
mental concepts and highlights state-of-the-art designs will be of great value to both graduate
students and industry engineers. While not an exhaustive text, we hope to illuminate funda-
mental concepts for the reader as well as identify trends and gaps in on-chip network research.
With the rapid advances in this field, we felt it was timely to update and review the state
of the art in this second edition. We introduce two new chapters at the end of the book, as will
be detailed below. roughout the book, in addition to updating the latest research in the past
years, we also expanded our coverage of fundamental concepts to include several research ideas
that have now made their way into products and, in our opinion, should be textbook concepts
that all on-chip network practitioners should know. For example, these fundamental concepts
include message passing, multicast routing, and bubble flow control schemes.
e structure of this book is as follows. Chapter 1 introduces on-chip networks in the
context of multi-core architectures and discusses their evolution from simple point-to-point
wires and buses for scalability.
Chapter 2 explains how networks fit into the overall system architecture of multi-core
designs. Specifically, we examine the set of requirements imposed by cache-coherence protocols
in shared memory chip multiprocessors, and contrast that with the requirements in message-
passing multi-cores. In addition to examining the system requirements, this chapter also de-
scribes the interface between the system and the network.
Once a context for the use of on-chip networks has been provided through a discussion of
system architecture, the details of the network are explored. As topology is often a first choice in
designing a network, Chapter 3 describes various topology trade-offs for cost and performance.
Given a network topology, a routing algorithm must be implemented to determine the path(s)
messages travel to be delivered throughout the network fabric; routing algorithms are explained
in Chapter 4. Chapter 5 deals with the flow control mechanisms employed in the network; flow
control specifies how network resources, namely buffers and links, are allocated to packets as
they travel from source to destination. Topology, routing, and flow control all factor into the
microarchitecture of the network routers. Details on various microarchitectural trade-offs and
design issues are presented in Chapter 6. is chapter includes the design of buffers, switches,
and allocators that comprise the router microarchitecture. Although power consumption can