ARM7TDMI-S内核详解：全面更新，纠正错误

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ARM7TDMI-S内核是ARM公司于1995年8月发布的的一款嵌入式处理器核心，由Advanced RISC Machines Ltd（ARM）设计并持有知识产权。ARM7TDMI全称为Advanced RISC Machine Technology for Digital Interface Microprocessor，它是一种针对数字接口应用设计的精简指令集计算机（RISC）架构，旨在提供高效的性能和低功耗特性。这款核心的主要特点包括： 1. **高性能与低功耗**：ARM7TDMI强调了在有限的硬件资源下实现高性能，适合对功耗敏感的应用，如移动设备、嵌入式系统和消费电子产品。 2. **开放访问**：虽然文档带有专属性的版权声明，表明复制或修改需获得ARM公司的许可，但该核心的信息对用户是开放的，以便于理解和使用。 3. **商标与权利保留**：ARM、ARMPowered、Embedded ICE、Black ICE和ICEbreaker都是ARM公司的商标，反映了其在嵌入式领域的领导地位。 4. **不断发展与改进**：ARM7TDMI作为一个不断演进的产品，可能会有持续的更新和优化，因此提供的规格和细节可能随时间而变化。 5. **免责声明**：尽管ARM以良好的意图提供了数据手册，但它不承担因使用手册信息、信息中的错误或遗漏，或者产品错误使用导致的任何损失或损害的责任。 6. **使用指南**：本数据手册仅作为用户使用该产品的参考工具，旨在帮助用户了解产品的特性和使用方法，但并不保证所有信息的准确性或适用于特定目的。 **总结**： ARM7TDMI-S内核是一款专为数字接口设计的高性能且低功耗的嵌入式处理器核心，其设计目的是为了满足对资源效率有高要求的现代电子设备。尽管存在版权和使用限制，但对于开发者来说，理解并遵循数据手册中的指导是关键，以便正确地集成和优化这一核心以满足项目需求。同时，使用者应意识到产品的不断改进，并在实际应用中注意可能存在的更新或兼容性问题。

Signal Description

ARM7TDMI Data Sheet

ARM DDI 0029E

2-2

Open Access

2.1 Signal Description

The following table lists and describes all the signals for the ARM7TDMI.

Transistor sizes

For a 0.6 µm ARM7TDMI:

INV4 driver has transistor sizes of p = 22.32 µm/0.6 µm

N = 12.6 µm/0.6 µm

INV8 driver has transistor sizes of p = 44.64 µm/0.6 µm

N = 25.2 µm/0.6 µm

Key to signal types

IC Input CMOS thresholds

P Power

O4 Output with INV4 driver

O8 Output with INV8 driver

Name Type Description

A[31:0]

Addresses

08 This is the processor address bus. If ALE (address latch enable)

is HIGH and APE (Address Pipeline Enable) is LOW, the

addresses become valid during phase 2 of the cycle before the

one to which they refer and remain so during phase 1 of the

referenced cycle. Their stable period may be controlled by ALE

or APE as described below.

ABE

Address bus enable

IC This is an input signal which, when LOW, puts the address bus

drivers into a high impedance state. This signal has a similar

effect on the following control signals: MAS[1:0], nRW, LOCK,

nOPC and nTRANS. ABE must be tied HIGH when there is no

system requirement to turn off the address drivers.

ABORT

Memory Abort

IC This is an input which allows the memory system to tell the

processor that a requested access is not allowed.

ALE

Address latch enable.

IC This input is used to control transparent latches on the address

outputs. Normally the addresses change during phase 2 to the

value required during the next cycle, but for direct interfacing to

ROMs they are required to be stable to the end of phase 2.

Taking ALE LOW until the end of phase 2 will ensure that this

happens. This signal has a similar effect on the following control

signals: MAS[1:0], nRW, LOCK, nOPC and nTRANS. If the

system does not require address lines to be held in this way,

ALE must be tied HIGH. The address latch is static, so ALE may

be held LOW for long periods to freeze addresses.

Table 2-1: Signal Description

Signal Description

ARM7TDMI Data Sheet

ARM DDI 0029E

2-3

Open Access

APE

Address pipeline enable.

IC When HIGH, this signal enables the address timing pipeline. In

this state, the address bus plus MAS[1:0], nRW, nTRANS,

LOCK and nOPC change in the phase 2 prior to the memory

cycle to which they refer. When APE is LOW, these signals

change in the phase 1 of the actual cycle. Please refer to

➲

Chapter 6, Memory Interface

for details of this timing.

BIGEND

Big Endian configuration.

IC When this signal is HIGH the processor treats bytes in memory

as being in Big Endian format. When it is LOW, memory is

treated as Little Endian.

BL[3:0]

Byte Latch Control.

IC These signals control when data and instructions are latched

from the external data bus. When BL[3] is HIGH, the data on

D[31:24] is latched on the falling edge of MCLK. When BL[2] is

HIGH, the data on D[23:16] is latched and so on. Please refer

➲

Chapter 6, Memory Interface

for details on the use of

these signals.

BREAKPT

Breakpoint.

IC This signal allows external hardware to halt the execution of the

processor for debug purposes. When HIGH causes the current

memory access to be breakpointed. If the memory access is an

instruction fetch, ARM7TDMI will enter debug state if the

instruction reaches the execute stage of the ARM7TDMI pipeline.

If the memory access is for data, ARM7TDMI will enter debug

state after the current instruction completes execution.This

allows extension of the internal breakpoints provided by the

ICEBreaker module. See

➲

Chapter 9, ICEBreaker Module

BUSDIS

Bus Disable

O This signal is HIGH when INTEST is selected on scan chain 0 or

4 and may be used to disable external logic driving onto the

bidirectional data bus during scan testing. This signal changes on

the falling edge of TCK.

BUSEN

Data bus configuration

IC This is a static configuration signal which determines whether the

bidirectional data bus, D[31:0], or the unidirectional data busses,

DIN[31:0] and DOUT[31:0], are to be used for transfer of data

between the processor and memory. Refer also to

➲

Chapter 6,

Memory Interface

When BUSEN is LOW, the bidirectional data bus, D[31:0] is

used. In this case, DOUT[31:0] is driven to value 0x00000000,

and any data presented on DIN[31:0] is ignored.

When BUSEN is HIGH, the bidirectional data bus, D[31:0] is

ignored and must be left unconnected. Input data and

instructions are presented on the input data bus, DIN[31:0],

output data appears on DOUT[31:0].

COMMRX

Communications Channel

Receive

O When HIGH, this signal denotes that the comms channel receive

buffer is empty. This signal changes on the rising edge of MCLK.

See

➲

9.11 Debug Communications Channel

on page 9-14

for more information on the debug comms channel.

Name Type Description

Table 2-1: Signal Description (Continued)

Signal Description

ARM7TDMI Data Sheet

ARM DDI 0029E

2-4

Open Access

COMMTX

Communications Channel

Transmit

O When HIGH, this signal denotes that the comms channel

transmit buffer is empty. This signal changes on the rising edge

of MCLK. See

➲

9.11 Debug Communications Channel

page 9-14 for more information on the debug comms channel.

CPA

Coprocessor absent.

IC A coprocessor which is capable of performing the operation that

ARM7TDMI is requesting (by asserting nCPI) should take CPA

LOW immediately. If CPA is HIGH at the end of phase 1 of the

cycle in which nCPI went LOW, ARM7TDMI will abort the

coprocessor handshake and take the undefined instruction trap.

If CPA is LOW and remains LOW, ARM7TDMI will busy-wait until

CPB is LOW and then complete the coprocessor instruction.

CPB

Coprocessor busy.

IC A coprocessor which is capable of performing the operation

which ARM7TDMI is requesting (by asserting nCPI), but cannot

commit to starting it immediately, should indicate this by driving

CPB HIGH. When the coprocessor is ready to start it should take

CPB LOW. ARM7TDMI samples CPB at the end of phase 1 of

each cycle in which nCPI is LOW.

D[31:0]

Data Bus.

These are bidirectional signal paths which are used for data

transfers between the processor and external memory. During

read cycles (when nRW is LOW), the input data must be valid

before the end of phase 2 of the transfer cycle. During write

cycles (when nRW is HIGH), the output data will become valid

during phase 1 and remain valid throughout phase 2 of the

transfer cycle.

Note that this bus is driven at all times, irrespective of whether

BUSEN is HIGH or LOW. When D[31:0] is not being used to

connect to the memory system it must be left unconnected. See

➲

Chapter 6, Memory Interface

DBE

Data Bus Enable.

IC This is an input signal which, when driven LOW, puts the data

bus D[31:0] into the high impedance state. This is included for

test purposes, and should be tied HIGH at all times.

DBGACK

Debug acknowledge.

04 When HIGH indicates ARM is in debug state.

DBGEN

Debug Enable.

IC This input signal allows the debug features of ARM7TDMI to be

disabled. This signal should be driven LOW when debugging is

not required.

DBGRQ

Debug request.

IC This is a level-sensitive input, which when HIGH causes

ARM7TDMI to enter debug state after executing the current

instruction. This allows external hardware to force ARM7TDMI

into the debug state, in addition to the debugging features

provided by the ICEBreaker block. See

➲

Chapter 9,

ICEBreaker Module

for details.

Name Type Description

Table 2-1: Signal Description (Continued)

Signal Description

ARM7TDMI Data Sheet

ARM DDI 0029E

2-5

Open Access

DBGRQI

Internal debug request

04 This signal represents the debug request signal which is

presented to the processor. This is the combination of external

DBGRQ, as presented to the ARM7TDMI macrocell, and bit 1 of

the debug control register. Thus there are two conditions where

this signal can change. Firstly, when DBGRQ changes, DBGRQI

will change after a propagation delay. When bit 1 of the debug

control register has been written, this signal will change on the

falling edge of TCK when the TAP controller state machine is in

the RUN-TEST/IDLE state. See

➲

Chapter 9, ICEBreaker

Module

for details.

DIN[31:0]

Data input bus

IC This is the input data bus which may be used to transfer

instructions and data between the processor and memory.This

data input bus is only used when BUSEN is HIGH. The data on

this bus is sampled by the processor at the end of phase 2 during

read cycles (i.e. when nRW is LOW).

DOUT[31:0]

Data output bus

08 This is the data out bus, used to transfer data from the processor

to the memory system. Output data only appears on this bus

when BUSEN is HIGH. At all other times, this bus is driven to

value 0x00000000. When in use, data on this bus changes

during phase 1 of store cycles (i.e. when nRW is HIGH) and

remains valid throughout phase 2.

DRIVEBS

Boundary scan

cell enable

04 This signal is used to control the multiplexers in the scan cells of

an external boundary scan chain. This signal changes in the

UPDATE-IR state when scan chain 3 is selected and either the

INTEST, EXTEST, CLAMP or CLAMPZ instruction is loaded.

When an external boundary scan chain is not connected, this

output should be left unconnected.

ECAPCLK

Extest capture clock

O This signal removes the need for the external logic in the test

chip which was required to enable the internal tristate bus during

scan testing. This need not be brought out as an external pin on

the test chip.

ECAPCLKBS

Extest capture clock for

Boundary Scan

04 This is a TCK2 wide pulse generated when the TAP controller

state machine is in the CAPTURE-DR state, the current

instruction is EXTEST and scan chain 3 is selected. This is used

to capture the macrocell outputs during EXTEST. When an

external boundary scan chain is not connected, this output

should be left unconnected.

ECLK

External clock output.

04 In normal operation, this is simply MCLK (optionally stretched

with nWAIT) exported from the core. When the core is being

debugged, this is DCLK. This allows external hardware to track

when the ARM7DM core is clocked.

EXTERN0

External input 0.

IC This is an input to the ICEBreaker logic in the ARM7TDMI which

allows breakpoints and/or watchpoints to be dependent on an

external condition.

Name Type Description

Table 2-1: Signal Description (Continued)

Signal Description

ARM7TDMI Data Sheet

ARM DDI 0029E

2-6

Open Access

EXTERN1

External input 1.

IC This is an input to the ICEBreaker logic in the ARM7TDMI which

allows breakpoints and/or watchpoints to be dependent on an

external condition.

HIGHZ 04 This signal denotes that the HIGHZ instruction has been loaded

into the TAP controller. See

➲

Chapter 8, Debug Interface

for

details.

ICAPCLKBS

Intest capture clock

04 This is a TCK2 wide pulse generated when the TAP controller

state machine is in the CAPTURE-DR state, the current

instruction is INTEST and scan chain 3 is selected. This is used

to capture the macrocell outputs during INTEST. When an

external boundary scan chain is not connected, this output

should be left unconnected.

IR[3:0]

TAP controller Instruction

04 These 4 bits reflect the current instruction loaded into the TAP

controller instruction register. The instruction encoding is as

described in

➲

8.8 Public Instructions

on page 8-9. These bits

change on the falling edge of TCK when the state machine is in

the UPDATE-IR state.

ISYNC

Synchronous interrupts.

IC When LOW indicates that the nIRQ and nFIQ inputs are to be

synchronised by the ARM core. When HIGH disables this

synchronisation for inputs that are already synchronous.

LOCK

Locked operation.

08 When LOCK is HIGH, the processor is performing a “locked”

memory access, and the memory controller must wait until LOCK

goes LOW before allowing another device to access the memory.

LOCK changes while MCLK is HIGH, and remains HIGH for the

duration of the locked memory accesses. It is active only during

the data swap (SWP) instruction. The timing of this signal may be

modified by the use of ALE and APE in a similar way to the

address, please refer to the ALE and APE descriptions. This

signal may also be driven to a high impedance state by driving

ABE LOW.

MAS[1:0]

Memory Access Size.

08 These are output signals used by the processor to indicate to the

external memory system when a word transfer or a half-word or

byte length is required. The signals take the value 10 (binary) for

words, 01 for half-words and 00 for bytes. 11 is reserved. These

values are valid for both read and write cycles. The signals will

normally become valid during phase 2 of the cycle before the one

in which the transfer will take place. They will remain stable

throughout phase 1 of the transfer cycle. The timing of the

signals may be modified by the use of ALE and APE in a similar

way to the address, please refer to the ALE and APE

descriptions. The signals may also be driven to high impedance

state by driving ABE LOW.

Name Type Description

Table 2-1: Signal Description (Continued)

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