ADS8588S：16位高速同步ADC，8通道数据手册

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“ADS8588S是一款16位高速8通道同步采样模数转换器（ADC），适用于单电源供电，具有双极性输入。该器件集成了PGA（可编程增益放大器）和数字滤波器功能，适用于多种数据采集系统。” ADS8588S是德州仪器（Texas Instruments）推出的一款高性能模拟到数字转换器，其主要特点包括： 1. **16位分辨率**：ADS8588S提供16位的精度，能够实现高分辨率的数据转换，适合对信号质量要求较高的应用。 2. **8通道同步采样**：该器件包含8个独立的输入通道（AIN_1P至AIN_8P及其对应的GND引脚），可以同时对多个信号进行采样，提高了系统的并行处理能力。 3. **双极性输入**：ADS8588S支持双极性输入信号，这意味着它可以处理正负电压范围内的信号，增强了其在各种信号条件下的适应性。 4. **SAR（逐次逼近寄存器）架构**：采用SAR架构，ADS8588S实现了高速转换，适用于需要快速数据采集的场景。 5. **2.5V参考电压**：内部集成的2.5VREF引脚提供了稳定的参考电压，确保了转换的准确性。 6. **PGA（可编程增益放大器）**：每个输入通道都配备了PGA，可以根据需要调整输入信号的增益，扩大或缩小输入信号的动态范围。 7. **数字滤波器**：内置的数字滤波器用于滤除高频噪声，提高信号质量，通常包括1M:3rd-Order LPF（低通滤波器）和Clamp功能。 8. **接口控制**：通过DB[15:0]引脚进行数字数据传输，DOUTA和DOUTB提供并行或串行（SER/PAR）输出，而控制信号如RD/SCLK、CS、RESET、CONVSTA、CONVSTB等则用于同步ADC操作。 9. **电源管理**：需要两个电源，即DVDD和AVDD，分别用于数字逻辑和模拟电路供电，同时有DGND、AGND和REFGND用于接地。 10. **状态和控制信号**：如FRSTDATA、STBY、REFCAPA、REFCAPB、REFSEL、BUSY等，这些信号用于监测ADC的状态和配置工作模式。 11. **安全注意事项**：该器件的使用应遵循 datasheet 中的安全提示，尤其在关键安全应用中需谨慎操作。 12. **技术文档支持**：用户可以通过Texas Instruments提供的产品目录、技术文档、工具软件以及社区支持获取更多信息和帮助。 ADS8588S是一款适用于多通道、高速、高精度数据采集的ADC，广泛应用于工业自动化、测试与测量、医疗设备等领域，具备出色的性能和灵活性。

ADS8588S

www.ti.com.cn

ZHCSFS8A –DECEMBER 2016–REVISED APRIL 2017

7.6 Timing Requirements: CONVST Control

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), BUSY load = 20 pF, V

and V

at datasheet limits, and f

SAMPLE

= 200 kSPS

(unless otherwise noted) (see Figure 1)

MIN NOM MAX UNIT

ACQ

Acquisition time:

BUSY falling edge to rising edge of trailing CONVSTA or CONVSTB

1 µs

PH_CN

CONVSTA, CONVSTB pulse high time 25 ns

PL_CN

CONVSTA, CONVSTB pulse low time 25 ns

SU_BSYCS

Setup time: BUSY falling to CS falling 0 ns

SU_RSTCN

Setup time: RESET falling to first rising edge of CONVSTA or CONVSTB 25 ns

PH_RST

RESET pulse high time 50 ns

D_CNAB

Delay between rising edges of CONVSTA and CONVSTB 500 µs

7.7 Timing Requirements: Data Read Operation

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), BUSY load = 20 pF, V

and V

at datasheet limits, and f

SAMPLE

= 200 kSPS

(unless otherwise noted) (see Figure 2)

MIN NOM MAX UNIT

DZ_CNCS

Delay between CONVSTA, CONVSTB rising edge to CS falling edge, start of

data read operation during conversion

10 ns

DZ_CSBSY

Delay between CS rising edge to BUSY falling edge, end of data read

operation during conversion

40 ns

SU_BSYCS

Setup time: BUSY falling edge to CS falling edge, start of data read operation

after conversion

0 ns

D_CSCN

Delay between CS rising edge to CONVSTA, CONVSTB rising edge, end of

data read operation after conversion

10 ns

7.8 Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V

and V

at datasheet limits,

and f

SAMPLE

= 200 kSPS (unless otherwise noted) (see Figure 3)

MIN NOM MAX UNIT

PH_CS

PH_RD

CS and RD high time 15 ns

PL_CS

PL_RD

CS and RD low time 15 ns

HT_RDDB

HT_CSDB

Hold time: RD and CS rising edge to DB[15:0] invalid 2.5 ns

ADS8588S

ZHCSFS8A –DECEMBER 2016–REVISED APRIL 2017

www.ti.com.cn

7.9 Timing Requirements: Parallel Data Read Operation, CS and RD Separate

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V

and V

at datasheet limits,

and f

SAMPLE

= 200 kSPS (unless otherwise noted) (see Figure 4)

MIN NOM MAX UNIT

SU_CSRD

Setup time: CS falling edge to RD falling edge 0 ns

HT_RDCS

Hold time: RD rising edge to CS rising edge 0 ns

PL_RD

RD low time 15 ns

PH_RD

RD high time 15 ns

HT_CSDB

Hold time: CS rising edge to DB[15:0] becoming invalid 6 ns

HT_RDDB

Hold time: RD rising edge to DB[15:0] becoming invalid 2.5 ns

7.10 Timing Requirements: Serial Data Read Operation

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), load on DOUTA, DOUTB, and FRSTDATA = 20 pF, V

and V

at datasheet

limits, and f

SAMPLE

= 200 kSPS (unless otherwise noted) (see Figure 5)

MIN NOM MAX UNIT

SCLK

SCLK time period 50 ns

PH_SCLK

SCLK high time 0.45 0.55 t

SCLK

PL_SCLK

SCLK low time 0.45 0.55 t

SCLK

HT_CKDO

Hold time: SCLK rising edge to DOUTA, DOUTB invalid 7 ns

SU_CSCK

Setup time: CS falling to first SCLK edge 8 ns

HT_CKCS

Hold time: last SCLK active edge to CS high 10 ns

7.11 Timing Requirements: Byte Mode Data Read Operation

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), load on DB[7:0] and FRSTDATA = 20 pF, V

and V

at datasheet limits, and

SAMPLE

= 200 kSPS (unless otherwise noted) (see Figure 6)

MIN NOM MAX UNIT

SU_CSRD

Setup time: CS falling edge to RD falling edge 0 ns

HT_RDCS

Hold time: RD rising edge to CS rising edge 0 ns

PL_RD

RD low time 15 ns

PH_RD

RD high time 15 ns

HT_CSDB

Hold time: CS rising edge to DB[15:0] becoming invalid 6 ns

HT_RDDB

Hold time: RD rising edge to DB[15:0] becoming invalid 2.5 ns

7.12 Timing Requirements: Oversampling Mode

MIN NOM MAX UNIT

HT_OS

Hold time: BUSY falling to OSx 20 ns

SU_OS

Setup time: BUSY falling to OSx 20 ns

(1) First conversion data must be discarded or RESET must be issued if the maximum timing is exceeded.

7.13 Timing Requirements: Exit Standby Mode

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C, AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), V

and V

at datasheet limits, and f

SAMPLE

= 200 kSPS (unless otherwise

noted) (see Figure 8)

MIN NOM MAX UNIT

D_STBYCN

Delay between STBY rising edge to CONVSTA or CONVSTB rising edge

(1)

100 µs

ADS8588S

www.ti.com.cn

ZHCSFS8A –DECEMBER 2016–REVISED APRIL 2017

(1) Excludes wake-up time for external reference device.

7.14 Timing Requirements: Exit Shutdown Mode

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), V

and V

at datasheet limits, and f

SAMPLE

= 200 kSPS (unless otherwise

noted) (see Figure 9)

MIN NOM MAX UNIT

D_SDRST

Delay between STBY rising edge to RESET rising edge

Internal reference mode 50

External reference mode

(1)

PH_RST

RESET high time 50 ns

D_RSTCN

Delay between RESET falling edge to CONVSTA or CONVSTB rising edge 25 µs

7.15 Switching Characteristics: CONVST Control

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), BUSY load = 20 pF, V

and V

at datasheet limits, and f

SAMPLE

= 200 kSPS

(unless otherwise noted) (see Figure 1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CYC

ADC cycle time period

No oversampling, parallel read, serial

read with both DOUTA and DOUTB

during conversion

µs

No oversampling, serial read after

conversion with both DOUTA and

DOUTB

9.7

No oversampling, serial read after

conversion with only DOUTA or

DOUTB

CONV

Conversion time: BUSY high time

No oversampling 3.7 3.8 3.9

µs

Oversampling by 2 8.4 8.8

Oversampling by 4 17.5 18.5

Oversampling by 8 36 38

Oversampling by 16 73 77

Oversampling by 32 148 155

Oversampling by 64 298 311

D_CNBSY

Delay between trailing rising edges of

CONVSTA or CONVSTB and BUSY

rising

15 ns

7.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together

minimum and maximum specifications are at T

= –40°C to +125°C, typical specifications are at T

= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V

REF

= 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V

and V

at datasheet limits,

and f

SAMPLE

= 200 kSPS (unless otherwise noted) (see Figure 3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

D_CSDB

D_RDDB

Delay time: CS and RD falling edge to

DB[15:0] becoming valid

(out of tri-state)

12 ns

D_CSFD

D_RDFD

Delay time: CS and RD falling edge to

FRSTDATA going high or low out of tri-

state

10 ns

DHZ_CSDB

DHZ_RDDB

Delay time: CS and RD rising edge to

DB[15:0] tri-state

12 ns

DHZ_CSFD

DHZ_RDFD

Delay time: CS and RD rising edge to

FRSTDATA tri-state

10 ns

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