MAX6955：集成I2C接口的LED驱动器与键盘扫描功能详解

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MAX6955是一款专为微处理器设计的紧凑型LED显示器驱动器，它通过I2C兼容的两线串行接口与各种7-segment、14-segment和16-segment LED显示器进行连接，支持多数字显示功能，最高可驱动16个7-segment数字、8个14-segment数字、8个16-segment数字或128个独立LED灯。这款驱动器的工作电压范围宽，可以从2.7V至5.5V，适合低功耗应用。驱动器的核心特性包括： 1. **I2C接口**：MAX6955采用了I2C标准，简化了与微处理器的通信，提高了系统集成度，减少了外部线路的数量。 2. **多类型显示器支持**：支持7-segment、14-segment和16-segment三种显示模式，能够灵活适应不同场景的需求。 3. **GPIO扩展**：内置五个I/O扩展器或通用输入/输出（GPIO）线路，部分甚至可以作为键盘扫描线，增强了输入设备的集成性。 4. **键盘扫描与去抖**：具备自动扫描和去抖功能，能处理多达32个开关的矩阵，提高键盘操作的可靠性和响应速度。 5. **内置字体库**：集成了全14-segment和16-segment的ASCII字符库，以及用于7-segment显示器的十六进制字体，便于快速显示文本信息。 6. **显示控制**：通过单个外部电阻设置每个数字段的最大电流，实现精细的亮度调节，共有16级亮度控制，可以独立调整每个数字的亮度。 7. **内存存储**：内置静态RAM用于存储每个数字字符，提高了数据处理效率和显示质量。 8. **低功耗设计**：MAX6955在优化设计下具有较低的功耗，适用于电池供电或者对能耗有限的应用场合。这款驱动器在工业自动化、嵌入式系统、仪表设备等领域的应用广泛，其易用性和高效性使其成为构建直观和多功能LED显示系统的理想选择。同时，配合提供的评估套件，开发人员可以更方便地进行原型设计和硬件调试。

MAX6955

2-Wire Interfaced, 2.7V to 5.5V

LED Display Driver with I/O

Expander and Key Scan

Maxim Integrated | 7www.maximintegrated.com

serial clock line (SCL) to achieve bidirectional commu-

nication between master(s) and slave(s). A master (typ-

ically a microcontroller) initiates all data transfers to and

from the MAX6955, and generates the SCL clock that

synchronizes the data transfer (Figure 2).

The MAX6955 SDA line operates as both an input and

an open-drain output. A pullup resistor, typically 4.7kΩ,

is required on the SDA. The MAX6955 SCL line oper-

ates only as an input. A pullup resistor, typically 4.7kΩ,

is required on SCL if there are multiple masters on the

2-wire interface, or if the master in a single-master sys-

tem has an open-drain SCL output.

Each transmission consists of a START condition

(Figure 3) sent by a master, followed by the MAX6955

7-bit slave address plus R/W bit (Figure 4), a register

address byte, 1 or more data bytes, and finally a STOP

condition (Figure 3).

Start and Stop Conditions

Both SCL and SDA remain high when the interface is

not busy. A master signals the beginning of a transmis-

sion with a START (S) condition by transitioning SDA

from high to low while SCL is high. When the master

has finished communicating with the slave, it issues a

STOP (P) condition by transitioning the SDA from low to

high while SCL is high. The bus is then free for another

transmission (Figure 3).

Bit Transfer

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable while SCL

is high (Figure 5).

Acknowledge

The acknowledge bit is a clocked 9th bit that the recipient

uses to handshake receipt of each byte of data (Figure 6).

Thus, each byte transferred effectively requires 9 bits. The

master generates the 9th clock pulse, and the recipient

pulls down SDA during the acknowledge clock pulse, such

that the SDA line is stable low during the high period of the

clock pulse. When the master is transmitting to the

MAX6955, the MAX6955 generates the acknowledge bit

because the MAX6955 is the recipient. When the

MAX6955 is transmitting to the master, the master gener-

ates the acknowledge bit because the master is the recipi-

ent.

Slave Address

The MAX6955 has a 7-bit-long slave address (Figure

4). The eighth bit following the 7-bit slave address is

the R/W bit. It is low for a write command, high for a

read command.

The first 3 bits (MSBs) of the MAX6955 slave address

are always 110. Slave address bits A3, A2, A1, and A0

are selected by the address input pins AD1 and AD0.

These two input pins can be connected to GND, V+,

SDA, or SCL. The MAX6955 has 16 possible slave

addresses (Table 5) and therefore a maximum of 16

MAX6955 devices can share the same interface.

DISPLAY TYPE

7 SEGMENT

(16-CHARACTER

HEXADECIMAL FONT)

14 SEGMENT/

16 SEGMENT

(104-CHARACTER ASCII FONT MAP)

DISCRETE LEDs

(DIRECT CONTROL)

Monocolor 16 8 128

Bicolor 8 4 64

Table 1. MAX6955 Drive Capability

1dp

2dp

g1 g2

dp dp

1e 1c

2f 2b

2e 2c

g1 g2

Figure 1. Segment Labeling for 7-Segment Display, 14-Segment Display, and 16-Segment Display

MAX6955

2-Wire Interfaced, 2.7V to 5.5V

LED Display Driver with I/O

Expander and Key Scan

Maxim Integrated | 8www.maximintegrated.com

Message Format for Writing

A write to the MAX6955 comprises the transmission of

the MAX6955’s slave address with the R/W bit set to

zero, followed by at least 1 byte of information. The first

byte of information is the command byte, which deter-

mines which register of the MAX6955 is to be written by

the next byte, if received. If a STOP condition is detect-

ed after the command byte is received, then the

MAX6955 takes no further action (Figure 7) beyond

storing the command byte.

Any bytes received after the command byte are data

bytes. The first data byte goes into the internal register of

the MAX6955 selected by the command byte (Figure 8).

If multiple data bytes are transmitted before a STOP

condition is detected, these bytes are generally stored

in subsequent MAX6955 internal registers because the

command byte address generally autoincrements

(Table 6) (Figure 9).

DIGIT O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18

0CCO— a1a2 b c d1d2 e f g1g2 h i j k l m dp

1 — CC1 a1 a2 b c d1 d2 e f g1 g2 h i j k l m dp

2 a1a2CC2— b c d1d2 e f g1g2 h i j k l m dp

3 a1 a2 — CC3 b c d1 d2 e f g1 g2 h i j k l m dp

4 a1a2 b cCC4—d1d2 e f g1g2 h i j k l mdp

5 a1 a2 b c — CC5 d1 d2 e f g1 g2 h i j k l m dp

6 a1 a2 b c d1 d2 CC6 — e f g1 g2 h i j k l m dp

7 a1 a2 b c d1 d2 — CC7 e f g1 g2 h i j k l m dp

DIGIT O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18

0 CCO — a — b c d — e f g1 g2 h i j k l m dp

1 — CC1 a — b c d — e f g1 g2 h i j k l m dp

2 a — CC2 — b c d — e f g1 g2 h i j k l m dp

3 a — — CC3 b c d — e f g1 g2 h i j k l m dp

4 a—b cCC4—d—e fg1g2h i j k l mdp

5 a — b c — CC5 d — e f g1 g2 h i j k l m dp

6 a—b c d—CC6—e fg1g2h i j k l mdp

7 a — b c d — — CC7 e f g1 g2 h i j k l m dp

Table 2. Connection Scheme for Eight 16-Segment Digits

Table 3. Connection Scheme for Eight 14-Segment Digits

DIGIT O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18

0, 0a CC0 — 1a — 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

1, 1a — CC1 1a — 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

2, 2a 1a — CC2 — 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

3, 3a 1a — — CC3 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

4, 4a 1a — 1b 1c CC4 — 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

5, 5a 1a — 1b 1c — CC5 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

6, 6a1a—1b1c1d1dpCC6— 1e 1f 1g2a2b2c2d2e 2f 2g2dp

7, 7a 1a — 1b 1c 1d 1dp — CC7 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

Table 4. Connection Scheme for Sixteen 7-Segment Digits

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