PXA3xx (88AP3xx) Processor Family
Vol. II: Memory Controller Configuration Developers Manual
Doc. No. MV-S301374-02 Rev. 2.0
Version -
Copyright © 2009 Marvell
Page 16 April 6, 2009 Released
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1.6 Operation
This section details the functions of the DMC, phase detector, calibration circuit and resistive
compensation.
1.6.1 Dynamic (SDRAM) Controller Functions
The DMC handles all DDR SDRAM memory transactions. The SDRAM interface supports 16-bit and
32-bit wide chip selects (partitions) of SDRAM. Each partition is allocated 512 Mbyte (PXA30x and
PXA31x) or 1 Gbyte (PXA32x only) of the internal memory map selected by the Section 1.9.2,
SDRAM Configuration Register (MDCNFG). However, the physical size of each partition depends on
the particular SDRAM type and configuration used, and the MDCNFG[DRAC] and MDCNFG[DCAC]
bits. The two SDRAM partitions must have the same timing parameter (tRAS, tRP, tRCD, tRC), the
same width (16 bit), and the same frequency.
Note
The density for each partition can be a different size.
1.6.1.1 SDRAM Refreshes
The DMC performs auto-refresh (CBR) during normal operation and supports self-refreshing
SDRAM during low-power modes in which the dynamic controller clocks and power are shut off. An
SDRAM Auto-powerdown mode is used to turn off SDCLK to the DRAM when the DRAM is not
being accessed. The SDRAM Refresh Control Register (MDREFR) sets the interval that the DMC
sends refresh commands to the DDR SDRAM. After reset (hardware or GPIO), the MDREFR
register must be written with the correct refresh interval that meets the DDR SDRAM requirements
specified in the device datasheet. Hardware automatically distributes the auto-refresh commands.
Consult the DDR SDRAM datasheet for the correct values for MDREFR[DRI].
1.6.1.2 Phase Detector Operation
The phase detector is used to for hardware calibrations of the delay line data strobes (DQSx). The
Out of Range interrupt (DMCIER[EORF]) must be enabled to interrupt the processor when the
phase detector value is found to be out of range. The phase detector compares the new value with
the old value residing in DMCISR[ORV] field. If the new value is found to be out of the range
specified by the DDR_HCAL[HCRNG], the new value determined by the phase detector is written to
DMCISR[ORV] field. The phase detector does not alter the strobe or the READ command. For more
information on enabling the phase detector, refer to Section 1.9.4, DDR Hardware Calibration
Register (DDR_HCAL).
1.6.1.3 Delay Line Calibration Operation
The phase detection circuit is used for hardware calibration to determine the number of delay-line
elements required to delay the DQSx strobe by ¼ of an SDCLK clock cycle across voltage and
temperature variations. DDR strobe calibration and configuration is performed by hardware. Four
separate delay lines exist to calibrate the eight possible strobes: 1 strobe / byte = 4 strobes.
Hardware calibration can be configured to interrupt the processor when a new delay-line value is
programmed or when the delay-line value falls out of range. If hardware reprograms the delay line,
an offset can be set by software and applied to the value determined by the phase detector. A status
register, DMCISR, is used to provide interrupt status and the results of the phase-detection circuits.
For more information on the hardware calibration settings, refer to the Section 1.9.4, DDR Hardware
Calibration Register (DDR_HCAL) and Section 1.9.5, DDR Write Strobe Calibration Register
(DDR_WCAL).