Marvell PXA3xx处理器系列：内存控制器配置手册（第二部分）

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第二部分

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"Marvell PXA3xx 处理器数据手册第二部分，涵盖了PXA30x、PXA31x和PXA320处理器系列的内存控制器配置开发者手册。文档版本为2.0，发布日期为2009年4月6日。" 在Marvell的PXA3xx处理器系列中，数据手册的第二部分主要聚焦于内存控制器的配置，这是理解和优化基于这些处理器的系统设计的关键元素。PXA3xx家族包括PXA30x（如88AP300、88AP301、88AP302、88AP303）、PXA31x（如88AP310、88AP311、88AP312）以及PXA320（如88AP320、88AP322）处理器。这些处理器被广泛用于移动设备和嵌入式系统，因其高性能和低功耗特性而受到青睐。内存控制器是处理器与内存系统交互的核心组件，它管理数据的读写操作，确保高效的数据传输。在本手册中，开发者可以找到关于内存接口规格、内存类型支持（如SDRAM、DDR SDRAM等）、内存时序设置、错误检测和纠正机制（如ECC）以及内存性能优化策略的详细信息。这些信息对于正确配置系统内存以达到最佳性能和稳定性至关重要。文档状态标识为“Preliminary”，意味着内容可能还在设计和开发的初期阶段，可能会有未经过完整技术审查和工程变更通知（ECN）流程的改动。因此，读者应该注意，Marvell有权在不预先通知的情况下修改这些规格。若要获取最新或更详细的信息，建议联系Marvell的现场应用工程师。文档中的注释和警告部分提醒开发者，不正确的配置或操作可能导致硬件损坏、软件问题或数据丢失，甚至有可能造成个人伤害。因此，在使用这些处理器进行系统设计时，必须严格遵循文档指南，并充分理解其中的风险。 PXA3xx数据手册第二部分提供了深入的内存控制器配置知识，对于设计和调试基于这些处理器的系统，以及提升系统的可靠性和性能具有重要指导价值。开发者需要密切关注Marvell的更新，以便及时获取最新的设计规格和建议。

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PXA3xx (88AP3xx) Processor Family

Vol. II: Memory Controller Configuration Developers Manual

Doc. No. MV-S301374-02 Rev. 2.0

Version -

Page 16 April 6, 2009 Released

1.6 Operation

This section details the functions of the DMC, phase detector, calibration circuit and resistive

compensation.

1.6.1 Dynamic (SDRAM) Controller Functions

The DMC handles all DDR SDRAM memory transactions. The SDRAM interface supports 16-bit and

32-bit wide chip selects (partitions) of SDRAM. Each partition is allocated 512 Mbyte (PXA30x and

PXA31x) or 1 Gbyte (PXA32x only) of the internal memory map selected by the Section 1.9.2,

SDRAM Configuration Register (MDCNFG). However, the physical size of each partition depends on

the particular SDRAM type and configuration used, and the MDCNFG[DRAC] and MDCNFG[DCAC]

bits. The two SDRAM partitions must have the same timing parameter (tRAS, tRP, tRCD, tRC), the

same width (16 bit), and the same frequency.

Note

The density for each partition can be a different size.

1.6.1.1 SDRAM Refreshes

The DMC performs auto-refresh (CBR) during normal operation and supports self-refreshing

SDRAM during low-power modes in which the dynamic controller clocks and power are shut off. An

SDRAM Auto-powerdown mode is used to turn off SDCLK to the DRAM when the DRAM is not

being accessed. The SDRAM Refresh Control Register (MDREFR) sets the interval that the DMC

sends refresh commands to the DDR SDRAM. After reset (hardware or GPIO), the MDREFR

specified in the device datasheet. Hardware automatically distributes the auto-refresh commands.

Consult the DDR SDRAM datasheet for the correct values for MDREFR[DRI].

1.6.1.2 Phase Detector Operation

The phase detector is used to for hardware calibrations of the delay line data strobes (DQSx). The

Out of Range interrupt (DMCIER[EORF]) must be enabled to interrupt the processor when the

phase detector value is found to be out of range. The phase detector compares the new value with

the old value residing in DMCISR[ORV] field. If the new value is found to be out of the range

specified by the DDR_HCAL[HCRNG], the new value determined by the phase detector is written to

DMCISR[ORV] field. The phase detector does not alter the strobe or the READ command. For more

information on enabling the phase detector, refer to Section 1.9.4, DDR Hardware Calibration

1.6.1.3 Delay Line Calibration Operation

The phase detection circuit is used for hardware calibration to determine the number of delay-line

elements required to delay the DQSx strobe by ¼ of an SDCLK clock cycle across voltage and

temperature variations. DDR strobe calibration and configuration is performed by hardware. Four

separate delay lines exist to calibrate the eight possible strobes: 1 strobe / byte = 4 strobes.

Hardware calibration can be configured to interrupt the processor when a new delay-line value is

programmed or when the delay-line value falls out of range. If hardware reprograms the delay line,

an offset can be set by software and applied to the value determined by the phase detector. A status

For more information on the hardware calibration settings, refer to the Section 1.9.4, DDR Hardware

Calibration Register (DDR_HCAL) and Section 1.9.5, DDR Write Strobe Calibration Register

(DDR_WCAL).

Dynamic Memory Controller

Operation

Version -

April 6, 2009 Released Page 17

Note

The phase detector must be enabled for S0/D0/C0 and is optional for S0/D0CS/C0.

Refer to section Section 1.8.5, Power Mode: S0/D0CS/C0 for more information on

S0/D0CS/C0 mode.

1.6.1.4 Resistive Compensation (RCOMP)

RCOMP dynamically compensates the DMC output drivers to account for variations in operating

conditions due to process, temperature, voltage, and board layout. These effects are measured

through a resistive mechanism referred to as a Resistive Dynamic Compensation feature, called

RCOMP. The DMC interface is designed to work with RCOMP enabled for all operations.

RCOMP tunes four separate output driver parameters:

 Pullup strength (PCODE)

 Pulldown strength (NCODE)

 Pullup slew rate (PSLEW)

 Pulldown slew rate (NSLEW)

These parameters are tuned separately for the groups defined in Table 2. The groups are adjusted

using the registers in Section 1.9.9, Programmable Buffer Strength and Slew Registers.

Resistive compensation can be divided into two sub-sequences:

1. RCOMP evaluation: When the conditions of the silicon are sampled and the new RCOMP value

is determined.

2. RCOMP update: When the output drivers receive the new PCODE, NCODE, PSLEW, and

NSLEW settings.

The RCOMP compensation sequence (evaluation and update) must be performed initially when the

processor resets and then periodically afterwards. The initial sequence is initiated directly by

software when programming the Section 1.9.8.2, Rcomp Control Register (RCOMP).

Periodic evaluation is based on a programmable RCOMP timer (RCOMP[REI]).For more information

on the procedures for setting up and programming the RCOMP circuits refer to 1.8 "Power Mode,

Reset and Frequency Changes"

1.6.1.5 Auto Powerdown Mode (APD)

Auto-powerdown is an automatic mechanism for minimizing power consumption in the processor. It

works by sending the “powerdown” command to SDRAM when no memory transaction requests are

Table 2: RCOMP Strength/Slew Control Groups

PAD_MA Strength/Slew Settings for MA[15:0]

PAD_MDMSB Strength/Slew Settings for MD[31:16]

PAD_MDLSB Strength/Slew Settings for MD[15:0], DQM<3:0>, and DQS<3:0>

PAD_DMEM Strength/Slew Settings for nSDCAS, nSDRAS, nSDWE, SDCKE,

and SDMA10

PAD_SDCLK Strength/Slew Settings for SDCLK[1:0]

PAD_SDCS Strength/Slew Settings for nSDCS[1:0]

PXA3xx (88AP3xx) Processor Family

Vol. II: Memory Controller Configuration Developers Manual

Doc. No. MV-S301374-02 Rev. 2.0

Version -

Page 18 April 6, 2009 Released

queued. This in turn shuts off the SDRAM internal clocking and input receivers, and for SSTL

receivers, allows the SSTL Vref to be powered down because SDRAM CKE and CLK pins used to

restart the SDRAM can sense LVCMOS levels. For the processor, APD mode is always enabled and

cannot be turned off by software.

1.6.2 SDRAM Memory Size Options

The SDRAM interface supports two partitions (chip selects) of SDRAM. Both partitions must have

the same timing requirements, and the same number of row and column address bits. Initialization

software must set up the Section 1.9.2, SDRAM Configuration Register (MDCNFG) with the SDRAM

timing category, number of row, column, and bank-address bits.

Figure 1, “16-bit External to Internal Address Mapping (Example) shows the bank/row/column

address multiplexing using two bank bits x 14 row bits x 11 column bits x 16 data bits. Figure 2,

“32-bit External to Internal Address Mapping (Example) shows the bank/row/column address

multiplexing using two bank bits x 14 row bits x 12 column bits x 32 data bits. All unused address bits

during CAS cycle are driven to 0; all unused bits during the RAS cycle are indeterminate and can be

driven to either 1 or 0.

When accessing SDRAM, only MA<11,9:0> are used for column addressing. SDMA<10> is driven

with 0 during column addressing, as required by SDRAMs. Bank address is used to inform the

SDRAM which bank is being read from, and they remain stable during column addressing.

Figure 1: 16-bit External to Internal Address Mapping (Example)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Column address

bank

address

row address

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

13 12 27 26 25 24 23 22 21 20 19 18 17 16 15 14

13 12 ‘0’ ‘0’ 11 ‘0’ 10 9 8 7 6 5 4 3 2 1

Bank Row Mapping

Bank Column Mapping

External Address pins

Internal 32 bit address for 2 bank bits x 14 row bits x 11 column bits x 16 data bits

Figure 2: 32-bit External to Internal Address Mapping (Example)

Bytes

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Column address

bank

address

row address

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 ‘0’ 13 12 ‘0’ 11 10 9 8 7 6 5 4 3 2

Bank Row Mapping

Bank Column Mapping

External Address pins

Internal 32 bit address for 2 bank bits x 14 row bits x 12 column bits x 32 data bits

Dynamic Memory Controller

Operation

Version -

April 6, 2009 Released Page 19

Table 3 shows how the internal address is mapped to the external address for both the RAS and

CAS cycle. The supported memory configuration options are included in this table. Fields denoted

with “?” mean the external address pin are indeterminate and can be driven with either a 1 or a 0.

1.6.2.1 SDRAM Burst Length, Burst Type, and Strength Settings

The DMC operates with a sequential burst type and a burst length of eight beats. The DMC does not

support other burst lengths or burst types. Output driver strength settings of SDRAMs depend on the

system topology.

1.6.2.2 Dynamic Memory Controller Memory Map

Table 4 defines the memory map for each DMC chip select. For more information on the memory

map for the processor refer to the Memory Map chapter in PXA3xx Processor Family Vol. I: System

and Timer Configuration Developers Manual.

1.6.2.3 Illegal Accesses and Nonexistent Memory

Accesses to or from non-existent memory are not detected in hardware. Indeterminate data is

returned when no memory is selected on a Read.

If a memory is not occupying all allocated megabytes of a partition but is occupying only a portion,

Reads and Writes from or to the unoccupied portion are processed as if the memory is occupying

the entire allocation of the memory partition but return indeterminate data. This is true for any

memory type.

Table 3: Processor Internal to External Addressing Options

Rows Columns External Address Pins at RAS Time External Address Pins at CAS Time

15141312111098765432101514131211109876543210

12 9 1110‘?’‘?’2322212019181716151413121110‘0’‘0’‘0’‘0’‘0’9 8 7 6 5 4 3 2 1

12 10 12 11 ‘?’ ‘?’ 24 23 22 21 20 19 18 17 16 15 14 13 12 11 ‘0’ ‘0’ ‘0’ ‘0’ 10 9 8 7 6 5 4 3 2 1

12 11 13 12 ‘?’ ‘?’ 25 24 23 22 21 20 19 18 17 16 15 14 13 12 ‘0’ ‘0’ 11 ‘0’ 10 9 8 7 6 5 4 3 2 1

13 9 11 10 ‘?’ 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ 9 8 7 6 5 4 3 2 1

13 10 1211‘?’252423222120191817161514131211‘0’‘0’ ‘0’‘0’ 109 8 7 6 5 4 3 2 1

13 11 1312‘?’262524232221201918171615141312‘0’‘0’11‘0’ 109 8 7 6 5 4 3 2 1

14 9 111025242322212019181716151413121110‘0’‘0’‘0’‘0’ ‘0’9 8 7 6 5 4 3 2 1

14 10 12 11 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 ‘0’ ‘0’ ‘0’ ‘0’ 10 9 8 7 6 5 4 3 2 1

14 11 13 12 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 ‘0’ ‘0’ 11 ‘0’ 10 9 8 7 6 5 4 3 2 1

Table 4: Dynamic Memory Controller Address Map

Chip Select Address Space

nSDCS<1> (PXA32x processor only) 0xC000_0000 – 0xFFFF_FFFF

nSDCS<1> (PXA30x and PXA31x Only) 0xC000_0000 – 0xDFFF_FFFF

nSDCS<0> (PXA32x processor only) 0x8000_0000 – 0xBFFF_FFFF

nSDCS<0> (PXA30x and PXA31x only) 0x8000_0000 – 0x9FFF_FFFF

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Marvell PXA3xx处理器系列：内存控制器配置手册（第二部分）

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