STM32G030x6/x8 Cortex-M0+ MCU: 高性能、低功耗微控制器

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"STM32G0系列是意法半导体（STMicroelectronics）推出的一款基于Arm Cortex-M0+内核的32位微控制器，适用于各种低功耗、高性能的应用场景。这款微控制器具备多种内存和外设接口，以及丰富的电源管理和时钟系统功能。" STM32G0系列的主要特性包括： 1. **核心处理器**: 配备了32位的Arm Cortex-M0+ CPU，工作频率最高可达64MHz，提供了高效的运算能力。 2. **工作温度范围**: 可在-40°C到85°C的温度范围内稳定工作，适应广泛的环境条件。 3. **内存配置**: 内置最大64KB的Flash存储器，支持数据保护；8KB的SRAM，并且具有硬件奇偶校验检查功能，确保数据安全。 4. **CRC计算单元**: 提供了错误检测和校验的能力，增强了系统的可靠性。 5. **电源管理**: 支持2.0V至3.6V的电压范围，具有POR/PDR（上电/掉电复位）功能，同时具备睡眠、停止和待机等低功耗模式。VBAT引脚可用于RTC（实时时钟）和备份寄存器，即使主电源断开也能保持运行。 6. **时钟系统**: 集成了4到48MHz的晶体振荡器，32kHz晶体振荡器带校准，以及16MHz的内部RC振荡器（可选PLL）和一个内部32kHz的RC振荡器，精度为±5%。 7. **I/O端口**: 提供最多44个快速I/O，所有I/O都能映射到外部中断向量，部分端口具有5V耐受能力，增强了与不同设备连接的兼容性。 8. **DMA控制器**: 5通道DMA控制器，支持灵活的映射，可以高效处理数据传输任务。 9. **模拟数字转换器（ADC）**: 12位ADC，转换时间为0.4μs，最多支持16个外部通道，通过硬件过采样可达到16位分辨率，转换范围为0到3.6V，适合各种模拟信号的采集。 10. **定时器**: 包括16位高级电机控制定时器和4个16位通用定时器，满足不同定时需求。此外，STM32G0系列还包含了丰富的通信接口，如USART（通用同步异步收发传输器），以及可能的SPI、I2C等，使其能够轻松连接各种外设和传感器。这个系列的微控制器广泛应用于嵌入式系统、物联网设备、智能家居、工业自动化以及消费电子等领域。

DS12991 Rev 3 15/93

STM32G030x6/x8 Functional overview

REF+

is delivered through VREF+ pin. On packages without VREF+ pin, V

REF+

internally connected with V

• V

CORE

An embedded linear voltage regulator is used to supply the V

CORE

internal digital

power. V

CORE

is the power supply for digital peripherals, SRAM and Flash memory.

The Flash memory is also supplied with V

Figure 2. Power supply overview

3.7.2 Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power

modes and ensuring proper operation upon power-on and power-down. It maintains the

device in reset when the supply voltage is below V

POR/PDR

threshold, without the need for

an external reset circuit.

3.7.3 Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator

(LPR), supply most of digital circuitry in the device.

The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power

sleep and Stop modes.

In Standby mode, both regulators are powered down and their outputs set in high-

impedance state, such as to bring their current consumption close to zero.

MSv47920V1

DDA

domain

RTC domain

A/D converter

Standby circuitry

(Wakeup, IWDG)

Voltage

regulator

Core

SRAM

Digital

peripherals

Low-voltage

detector

LSE crystal 32.768 kHz osc

BKP registers

RCC BDCR register

RTC and TAMP

I/O ring

CORE

domain

Temp. sensor

Reset block

PLL, HSI

Flash memory

DDIO1

VREF+

domain

CORE

VSS/VSSA

VDD/VDDA

VBAT

DDA

REF+

SSA

DDIO1

domain

Functional overview STM32G030x6/x8

16/93 DS12991 Rev 3

3.7.4 Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the

user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

CORE

supplied by the low-power regulator to minimize the

regulator's operating current. The code can be executed from SRAM or from Flash,

and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can

be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the Low-

power run mode.

• Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while

retaining the SRAM and register contents. All clocks in the V

CORE

domain are stopped.

The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are

disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with

RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,

so as to get clock for processing the wakeup event. The main regulator remains active

in Stop 0 mode while it is turned off in Stop 1 mode.

• Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR

always active in this mode. The main regulator is switched off to power down V

CORE

domain. The low-power regulator is switched off. The PLL, as well as the HSI16 RC

oscillator and the HSE crystal oscillator are also powered down. The RTC can remain

active (Standby mode with RTC, Standby mode without RTC).

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor

shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost except for registers in the RTC

domain and standby circuitry.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE

(CSS on LSE).

DS12991 Rev 3 17/93

STM32G030x6/x8 Functional overview

3.7.5 Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce

power consumption. In addition, when the reset source is internal, the built-in pull-up

resistor on NRST pin is deactivated.

3.7.6 VBAT operation

The V

BAT

power domain, consuming very little energy, includes RTC, and LSE oscillator and

backup registers.

In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for

example, an external battery or an external supercapacitor. Two anti-tamper detection pins

are available.

The RTC domain can also be supplied from VDD/VDDA pin.

By means of a built-in switch, an internal voltage supervisor allows automatic switching of

RTC domain powering between V

and voltage from VBAT pin to ensure that the supply

voltage of the RTC domain (V

BAT

) remains within valid operating conditions. If both voltages

are valid, the RTC domain is supplied from VDD/VDDA pin.

An internal circuit for charging the battery on VBAT pin can be activated if the V

voltage is

within a valid range.

Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT

mode, as in that mode the V

is not within a valid range.

3.8 Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep and Stop

modes.

Table 4. Interconnect of STM32G030x6/x8 peripherals

Interconnect source

Interconnect

destination

Interconnect action

Run

Low-power run

Sleep

Low-power sleep

Stop

TIMx

TIMx Timer synchronization or chaining Y Y -

ADCx Conversion triggers Y Y -

DMA Memory-to-memory transfer trigger Y Y -

ADCx TIM1 Timer triggered by analog watchdog Y Y -

RTC

TIM16 Timer input channel from RTC events Y Y -

DS12991 Rev 3 19/93

STM32G030x6/x8 Functional overview

3.9 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and

the peripherals. It also manages clock gating for low-power modes and ensures clock

robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

• System clock source: three different sources can deliver SYSCLK system clock:

– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It

can supply clock to system PLL. The HSE can also be configured in bypass mode

for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can

supply clock to system PLL.

– System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or

HSI16 clocks.

• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive

capability modes. The LSE can also be configured in bypass mode for using an

external clock.

– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to

clock an independent watchdog.

• Peripheral clock sources: several peripherals (I2S, USARTs, I2Cs, ADC) have their

own clock independent of the system clock.

• Clock security system (CSS): in the event of HSE clock failure, the system clock is

automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE

clock failure can also be detected and generate an interrupt. The CCS feature can be

enabled by software.

• Clock output:

– MCO (microcontroller clock output) provides one of the internal clocks for

external use by the application

– LSCO (low speed clock output) provides LSI or LSE in all low-power modes

(except in VBAT operation).

Several prescalers allow the application to configure AHB and APB domain clock

frequencies, 64 MHz at maximum.

3.10 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of

the GPIO pins are shared with special digital or analog functions.

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