IEEE 1801标准：低功耗集成电路设计与验证

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"IEEE标准用于低功耗集成电路的设计与验证，UPF标准/IEEE.P1801" IEEE Std 1801，也被称为统一功率格式（UPF），是国际电气和电子工程师协会（IEEE）制定的一个标准，专门针对低功耗集成电路（IC）的设计和验证。这个标准在2013年进行了修订，即IEEE Std 1801-2013，它是对2009年版本的更新。该标准由IEEE计算机学会的设计自动化委员会和IEEE标准协会企业顾问组共同赞助。低功耗设计对于现代电子设备至关重要，尤其是在移动设备、物联网设备以及各种能源敏感的应用中。UPF标准提供了一种框架，使设计者能够系统地考虑和实施电源管理策略，包括电源域划分、动态电压和频率调整（DVFS）、多电压岛、时钟关断、门控时钟、以及电源门控等技术，以实现高效能和低功耗的集成电路设计。 UPF标准允许设计师在硬件描述语言（HDL）级别定义和实现电源管理行为，如电压域和电源网路，以及电源状态转换。这使得在设计流程早期就能进行功耗分析和优化，从而降低功耗并提高电路性能。此外，UPF还支持协同设计，即同时处理逻辑设计和电源管理设计，确保了设计的一致性和完整性。 IEEE Std 1801-2013的修订可能包含了对之前版本的改进，比如增强的功耗模型、更灵活的电源架构定义、对新工艺节点的支持，以及与其他EDA工具和标准（如SystemVerilog）的更好集成。这些改进旨在提高低功耗设计的效率，降低功耗预测的不确定性，并促进整个半导体行业的标准化。通过遵循IEEE Std 1801标准，设计团队可以确保其低功耗集成电路的验证过程更加规范化，从而减少设计错误，提高产品的质量和可靠性。此外，这个标准还促进了不同设计团队之间的沟通和协作，因为它们都使用了相同的方法论和格式来描述电源管理特性。 IEEE Std 1801-2013是集成电路设计领域的一个关键参考，对于那些致力于开发节能电子产品的公司，如Advanced Micro Devices（AMD），此标准具有重要的指导意义。它帮助设计人员实现创新的低功耗解决方案，满足不断增长的市场需求，同时推动整个电子行业的绿色化进程。

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IEEE Standard for Design and

Verification of

Low-Power Integrated Circuits

IMPORTANT NOTICE: This standard is not intended to ensure safety, security, health, or

environmental protection in all circumstances. Implementers of the standard are responsible for

determining appropriate safety, security, environmental, and health practices or regulatory requirements.

This IEEE document is made available for use subject to important notices and legal disclaimers. These

notices and disclaimers appear in all publications containing this document and may be found under the

heading “Important Notice” or “Important Notices and Disclaimers Concerning IEEE Documents.”

They can also be obtained on request from IEEE or viewed at http://standards.ieee.org/IPR/

disclaimers.html.

1. Overview

1.1 Scope

This standard establishes a format used to define the low-power design intent for electronic systems and

electronic intellectual property (IP). The format provides the ability to specify the supply network, switches,

isolation, retention, and other aspects relevant to power management of an electronic system. The standard

defines the relationship between the low-power design specification and the logic design specification

captured via other formats [e.g., standard hardware description languages (HDLs)].

1.2 Purpose

The standard provides portability of low-power design specifications that can be used with a variety of

commercial products throughout an electronic system design, analysis, verification, and implementation

flow.

1.3 Key characteristics of the Unified Power Format

The Unified Power Format (UPF) provides the ability for electronic systems to be designed with power as a

key consideration early in the process. UPF accomplishes this by allowing the specification of what was

traditionally physical implementation-based power information early in the design process—at the register

transfer level (RTL) or earlier. Figure 1

shows UPF supporting the entire design flow. UPF provides a

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IEEE Std 1801-2013

IEEE STANDARD FOR DESIGN AND VERIFICATION OF LOW-POWER INTEGRATED CIRCUITS

consistent format to specify power design information that may not be easily specifiable in an HDL or when

it is undesirable to directly specify the power semantics in an HDL, as doing so would tie the logic

specification directly to a constrained power implementation. UPF specifies a set of HDL attributes and

HDL packages to facilitate the expression of power intent in HDL when appropriate (see Table 4

and

Annex B

). UPF also defines consistent semantics across verification and implementation, i.e., what is

implemented is the same as what has been verified.

Figure 1—UPF tool flow

As indicated in Figure 1, UPF files are part of the design source and, when combined with the HDL,

represent a complete design description: the HDL describing the logical intent and the UPF describing the

power intent. Combined with the HDL, the UPF files are used to describe the intent of the designer. This

collection of source files is the input to several tools, e.g., simulation tools, synthesis tools, and formal

verification tools. UPF supports the successive refinement methodology (see 4.8

) where power intent

information will grow along the design flow to provide needed information for each design stage.

— Simulation tools can read the HDL/UPF design input files and perform RTL power-aware

simulation. At this stage, the UPF may only contain abstract models such as power domains and

supply sets without the need to create the power and ground network and implementation details.

— Synthesis tools can read the HDL/UPF design input files and produce a netlist. The tool or user may

produce a new UPF fileset that, combined with the netlist, represents a further refined version of

same design.

— In those cases where design object names change, a UPF file with the new names is needed. A UPF-

aware logical equivalence checker can read the full design and UPF filesets and perform the checks

to ensure power-aware equivalence.

— Place and route tools read both the netlist and the UPF files and produce a physical netlist,

potentially including an output UPF file.

Synthesis

UPF

HDL

(RTL)

P & R

UPF

Verilog

(Netlist)

UPF

Verilog

(Netlist)

Sim

lati

cal Eq

iva

enc

Check

ng, ..

Synthesis

UPF

HDL

(RTL)

P & R

UPF

Verilog

(Netlist)

UPF

Verilog

(Netlist)

Sim

lati

cal Eq

iva

enc

Check

ng, ..

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IEEE Std 1801-2013

IEEE STANDARD FOR DESIGN AND VERIFICATION OF LOW-POWER INTEGRATED CIRCUITS

UPF is a concise power intent specification capability. Power intent can be easily specified over many

elements in the design. A UPF specification can be included with the other deliverables of IP blocks and

reused along with the other delivered IP. UPF supports various methodologies through carefully defined

semantics, flexibility in specification, and, when needed, defined rational limitations that facilitate

automation in verification and implementation (see Annex E

A UPF specification defines how to create a supply network to supply power to each instance, how the

individual supply nets behave with respect to one another, and how the logic functionality is extended to

support dynamic power switching to these logic instances. By controlling the states and voltages of the

supplies provided to the supply network, and by controlling the states of power switches that are part of the

supply network, the power management logic of a system can cause each functional region to receive the

power required to complete its computational tasks in a timely manner.

1.4 Use of color in this standard

This standard uses a minimal amount of color to enhance readability. The coloring is not essential and does

not affect the accuracy of this standard when viewed in pure black and white. The places where color is used

are the following:

— Cross references that are hyperlinked to other portions of this standard are shown in underlined-blue

text (hyperlinking works when this standard is viewed interactively as a PDF file).

— Syntactic keywords and tokens in the formal language definitions are shown in boldface-red text.

— Command arguments that can be provided incrementally (layered) are shown in boldface-green

text. See also 5.11

— Syntactic keywords and tokens that have been explicitly identified as legacy or deprecated constructs

(see 6.1

) may be shown in brown text.

1.5 Contents of this standard

The organization of the remainder of this standard is as follows:

— Clause 2

provides references to other applicable standards that are presumed or required for this

standard.

— Clause 3

defines terms and acronyms used throughout the different specifications contained in this

standard.

— Clause 4

describes the basic concepts underlying UPF.

— Clause 5

describes the language basics for UPF and its commands.

— Clause 6

details the syntax and semantics for each UPF power intent command.

— Clause 7

details the syntax and semantics for each UPF power-management cell command.

— Clause 8

defines a reference model for UPF command processing.

— Clause 9

defines simulation semantics for various UPF commands.

— Annexes. Following Clause 9

are a series of annexes.

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IEEE Std 1801-2013

IEEE STANDARD FOR DESIGN AND VERIFICATION OF LOW-POWER INTEGRATED CIRCUITS

2. Normative references

The following referenced documents are indispensable for the application of this standard (i.e., they must be

understood and used, so each referenced document is cited in the text and its relationship to this document is

explained). For dated references, only the edition cited applies. For undated references, the latest edition of

the referenced document (including any amendments or corrigenda) applies.

IEC 61691-1-1/IEEE Std 1076™, Behavioural languages—Part 1: VHDL Language Reference Manual.

IEEE Std 1800™, IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and

Verification Language.

3. Definitions, acronyms, and abbreviations

For the purposes of this document, the following terms and definitions apply. The IEEE Standards

Dictionary Online [B1]

should be consulted for terms not defined in this clause.

4, 5

Certain terms in this

standard reflect their corresponding definitions in IEEE Std 1800 or IEC 61691-1-1/IEEE Std 1076, or they

are listed in Annex A

3.1 Definitions

active component: A component that contains one or more input receivers and one or more output drivers

whose values are functions of the inputs, but whose inputs and outputs are not directly connected; or any

HDL construct(s) that synthesize(s) to an active component.

active control signal: A control signal that is currently presenting the value (level) or transition (edge) that

enables or triggers an active component to operate in a particular manner.

active power state: A power state whose logic expression and, if present, supply expression evaluate to

True at a given time.

activity: Any change in the value of a net, regardless of whether that change is propagated to an output.

ancestor: Any instance between the current scope in the logic hierarchy and its root scope. When the

current scope is a top-level module, it does not have any ancestors. See also: descendant.

anonymous object: An object that is not named in the context of UPF. Implementations may assign a legal

name, but such names are not visible in the UPF context.

balloon latch: A retention element style in which a register’s value is saved to a dedicated latch at power-

down and the latch value is restored to the register at power-up.

boundary instance: An instance that has no parent or whose parent is in a different power domain.

IEC publications are available from the International Electrotechnical Commission (http://www.iec.ch/). IEC publications are also

available in the United States from the American National Standards Institute (http://www.ansi.org/).

IEEE publications are available from The Institute of Electrical and Electronics Engineers (http://standards.ieee.org/).

The IEEE standards or products referred to in this clause are trademarks of The Institute of Electrical and Electronics Engineers, Inc.

IEEE Standards Dictionary Online subscription is available at:

http://www.ieee.org/portal/innovate/products/standard/standards_dictionary.html

The numbers in brackets correspond to those of the bibliography in Annex A.

Information on references can be found in Clause 2.

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