BCM5396交换芯片详解：16端口单片SerDes千兆以太网解决方案

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"BCM5396是一款单芯片16端口SerDes千兆交换机，适用于桌面交换解决方案或WebSmart应用，具有低功耗、高性能的特点。它集成了高速交换系统所需的所有功能，包括包缓冲区、媒体访问控制器（MACs）、地址管理以及无阻塞交换控制器。此芯片符合IEEE 802.3系列标准，确保与所有标准以太网、快速以太网和千兆以太网设备的兼容性。内置的1.25G SerDes接口减少了外部组件的需求，提高了设计的集成度和成本效益。" BCM5396交换芯片是博通（Broadcom）公司推出的一款高性能、低功耗的网络交换解决方案，特别适合于桌面级交换机和WebSmart应用。该芯片的核心特性包括： 1. **16个1.25G SerDes/SGMII端口接口**：这使得BCM5396能够直接连接到外部的千兆物理层（PHY）设备或光纤模块，提供高速的数据传输能力。 2. **高度集成的设计**：将高速交换系统所需的全部功能，如包缓冲、MACs、地址管理和无阻塞交换控制器等集成在一个单一的0.13微米CMOS芯片上，降低了系统复杂性和成本。 3. **遵循IEEE标准**：BCM5396符合IEEE 802.3系列规范，包括802.3u（快速以太网）、802.3ab（千兆以太网）和802.3x（流量控制），并支持PAUSE帧和自动协商功能，确保与各种标准以太网设备的互操作性。 4. **无阻塞交换控制器**：提供线速交换能力，确保在网络负载高峰期也能实现数据的高效传输，不会出现数据包丢失或延迟。 5. **内置1.25G SerDes**：这减少了对外部SerDes组件的需求，简化了设计，同时也提高了系统的可靠性和能效。在实际应用中，BCM5396可以用于构建高效能、低成本的网络基础设施，如企业内部的局域网交换机、数据中心的边缘交换机或者针对家庭和小型办公室的智能网络设备。由于其高度集成和广泛的兼容性，开发者可以轻松地利用BCM5396来开发各种网络产品，同时保持良好的性能和较低的功耗。在使用BCM5396时，开发者需要注意配置MAC地址表、设置流控策略、优化包缓冲区的使用，以及确保与不同类型的PHY设备正确连接和通信。此外，理解并利用芯片提供的高级特性，如QoS（服务质量）和VLAN（虚拟局域网）支持，可以帮助构建更高效且灵活的网络环境。

CONFIDENTIAL FOR KAI YANG AT AVNET ASIA PTE LTD

12/26/2013 FB1PM

List of Figures BCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch

October 4, 2013 • 5396-DS114-R Page 16

BROADCOM CONFIDENTIAL

List of Figures

Figure 1: Functional Block Diagram....................................................................................................................2

Figure 2: Priority Packet Mapping Flow ...........................................................................................................27

Figure 3: VLAN Table Organization...................................................................................................................31

Figure 4: Bucket Flow .......................................................................................................................................34

Figure 5: Mirror Filter Flow ..............................................................................................................................36

Figure 6: Address Table Organization...............................................................................................................39

Figure 7: TXQ and Buffer Tag Structure............................................................................................................54

Figure 8: RvMII Port Connections.....................................................................................................................57

Figure 9: Normal SPI Command Byte ...............................................................................................................61

Figure 10: Fast SPI Command Byte...................................................................................................................61

Figure 11: SPI Serial Interface Write Operation ...............................................................................................62

Figure 12: SPI Serial Interface Read Operation ................................................................................................62

Figure 13: Normal SPI Mode Read Flow Chart .................................................................................................63

Figure 14: Normal SPI Mode Write Flow Chart ................................................................................................65

Figure 15: Timing Example ...............................................................................................................................66

Figure 16: Serial EEPROM Connection .............................................................................................................67

Figure 17: MDC/MDIO Interface ......................................................................................................................68

Figure 18: Read Access to Switch via Pseudo-PHY (PHY ADD = 1_1110) MDC[0]/MDIO[0] Path.....................69

Figure 19: Write Access to Switch via Pseudo-PHY (PHY ADD = 1_1110) MDC[0]/MDIO[0] Path....................70

Figure 20: Pseudo-PHY MII Register Map.........................................................................................................71

Figure 21: Pins Top View ..................................................................................................................................88

Figure 22: Reset and Clock Timing .................................................................................................................182

Figure 23: RvMII Mode Output Timings .........................................................................................................183

Figure 24: RvMII Mode Input Timings ............................................................................................................183

Figure 25: RGMII Output Timing (Normal Mode)...........................................................................................184

Figure 26: RGMII Output Timing (Delayed Mode)..........................................................................................185

Figure 27: RGMII Input Timing (Normal Mode)..............................................................................................186

Figure 28: RGMII Input Timing (Delayed Mode).............................................................................................187

Figure 29: GMII Output Timing.......................................................................................................................188

Figure 30: GMII Input Timing..........................................................................................................................188

Figure 31: Serial Interface Output Timing ......................................................................................................189

Figure 32: Serial Interface Input Timing .........................................................................................................190

Figure 33: MDC/MDIO Timing ........................................................................................................................190

Figure 34: Serial LED Interface Timing............................................................................................................191

Figure 35: SPI Timings, SS

Asserted During SCK High .....................................................................................192

CONFIDENTIAL FOR KAI YANG AT AVNET ASIA PTE LTD

12/26/2013 FB1PM

List of Tables BCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch

October 4, 2013 • 5396-DS114-R Page 18

BROADCOM CONFIDENTIAL

List of Tables

Table 1: Frame Priority Decision Tree Summary ..............................................................................................30

Table 2: Bucket Bit Rate ...................................................................................................................................35

Table 3: Unicast Forward Field Definitions.......................................................................................................41

Table 4: Address Table Entry for Unicast Address............................................................................................41

Table 5: Multicast Forward Field Definitions ...................................................................................................43

Table 6: Address Table Entry for Multicast ARL Address..................................................................................43

Table 7: Behavior for Reserved Multicast Addresses.......................................................................................44

Table 8: Spanning Tree State............................................................................................................................49

Table 9: SGMII and SerDes Auto-Negotiation ..................................................................................................56

Table 10: Transmit/Receive Frame Format Over Management Port ...............................................................58

Table 11: OPCODE Field in BRCM Tag for Management Port Frame ...............................................................58

Table 12: IMP Broadcom TAG RX from CPU .....................................................................................................59

Table 13: IMP Broadcom TAG TX to CPU..........................................................................................................60

Table 14: EEPROM_EXT[1:0] Settings...............................................................................................................66

Table 15: EEPROM Header Format...................................................................................................................67

Table 16: EEPROM Contents ............................................................................................................................67

Table 17: Pseudo-PHY MII Register Definitions................................................................................................72

Table 18: MII Management Frame Format ......................................................................................................73

Table 19: Serial LED Mode Matrix ....................................................................................................................74

Table 20: Serial LED Status Types .....................................................................................................................75

Table 21: Load Meter LED Decode ...................................................................................................................75

Table 22: I/O Signal Type Definitions ...............................................................................................................77

Table 23: Signal Descriptions............................................................................................................................78

Table 24: Pin Assignment (Listed by Pin Number) ...........................................................................................84

Table 25: Pin Assignment (Listed by Signal Name)...........................................................................................86

Table 26: Global Page Register Map.................................................................................................................89

Table 27: Control Registers (Page 00h) ............................................................................................................92

Table 28: 10/100/1000 Port Control Register (Page 00h: Address 00h–0Fh) ..................................................94

Table 29: IMP Port Control Register (Page 00h: Address 10h).........................................................................94

Table 30: Switch Mode Register (Page 00h: Address 20h)...............................................................................95

Table 31: LED A Register (Page 00h: Address 24h–25h)...................................................................................96

Table 32: New Control Register (Page 00h: Address 3Bh) ...............................................................................96

Table 33: Reserved Multicast Register (Page 00h: Address 50h) .....................................................................97

Table 34: Load Meter Update Rate Control Register (Page 00h: Address 51h) ...............................................97

Table 35: Unicast Lookup Failed Forward Map Register (Page 00h: 54h–57h)................................................98

CONFIDENTIAL FOR KAI YANG AT AVNET ASIA PTE LTD

12/26/2013 FB1PM

List of Tables BCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch

October 4, 2013 • 5396-DS114-R Page 19

BROADCOM CONFIDENTIAL

Table 36: Multicast Lookup Failed Forward Map Register (Page 00h: Address 58h–5Bh)...............................98

Table 37: Port N State Override Register (Page 00h: Address 60–6Fh)............................................................98

Table 38: Port 16 (IMP) State Override Register (Page 00h: Address 70h) ......................................................99

Table 39: 802.1X Control Register 1 (Page 00h: Address 77h) .......................................................................100

Table 40: 802.1X Control Register 2 (Page 00h: Address 78h–7Bh)...............................................................100

Table 41: SerDes Default Values Register (Page 00h: Address 80h–83h) ......................................................100

Table 42: SerDes Select Early Version of CRS and COL Register (Page 00h: Address 84h–85h).....................101

Table 43: External PHY Scan Control Register (Page 00h: Address 86h) ........................................................101

Table 44: Fast Aging Control Register (Page 00h: Address 88h) ....................................................................102

Table 45: Fast Aging Port Register (Page 00h: Address 89h)..........................................................................102

Table 46: Fast Aging VID Register (Page 00h: Address 138d–139d, 8Ah–8Bh) ..............................................102

Table 47: Pause Frame Detection Control Register (Page 00h: Address 90h)................................................103

Table 48: Status Registers (Page 01h) ............................................................................................................104

Table 49: Link Status Summary Register (Page 01h: Address 00h–03h) ........................................................105

Table 50: Link Status Change Register (Page 01h: Address 04h–07h)............................................................105

Table 51: Port Speed Summary Register (Page 01h: Address 08h–0Fh) ........................................................105

Table 52: Duplex Status Summary Register (Page 01h: Address 10h–13h) ...................................................106

Table 53: TX PAUSE Status Summary Register (Page 01h: Address 14h–17h) ...............................................106

Table 54: RX PAUSE Status Summary Register (Page 01h: Address 18h–1Bh)...............................................106

Table 55: Port N PHY Status Register (Page 01h: Address 20–2Fh)................................................................107

Table 56: SerDes Signal Detect Status Register (Page 01h: Address 40h)......................................................107

Table 57: BIST Status Register (Page 01h, Address 46h) ................................................................................107

Table 58: Strap Value Register (Page 01h: Address 70h–73h) .......................................................................108

Table 59: Management Mode Registers (Page 02h) ......................................................................................109

Table 60: Global Management Configuration Register (Page 02h: Address 00h) ..........................................109

Table 61: Aging Time Control Register (Page 02h: Address 0Ch–0Fh) ...........................................................110

Table 62: Mirror Capture Control Register (Page 02h: Address 10h–11h).....................................................110

Table 63: Ingress Mirror Control Register (Page 02h: Address 12h–15h) ......................................................111

Table 64: Ingress Mirror Divider Register (Page 02h: Address 16h–17h).......................................................111

Table 65: Egress Mirror Control Register (Page 02h: Address 1Ch–1Fh) .......................................................112

Table 66: Model ID Register (Page 02h: Address 30h) ...................................................................................112

Table 67: Revision ID Register (Page 02h: Address 40h) ................................................................................112

Table 68: ARL Control Registers (Page 04h) ...................................................................................................113

Table 69: Global ARL Configuration Register (Page 04h: Address 00h)..........................................................113

Table 70: BPDU Multicast Address Register (Page 04h: Address 04h–09h)...................................................114

Table 71: Multiport Address 1 Register (Page 04h: Address 10h–15h)..........................................................114

CONFIDENTIAL FOR KAI YANG AT AVNET ASIA PTE LTD

12/26/2013 FB1PM

List of Tables BCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch

October 4, 2013 • 5396-DS114-R Page 20

BROADCOM CONFIDENTIAL

Table 72: Multiport Vector 1 Register (Page 04h: Address 16h–19h)............................................................114

Table 73: Multiport Address 2 Register (Page 04h: Address 20h–25h)..........................................................115

Table 74: Multiport Vector 2 Register (Page 04h: Address 26h–29h)............................................................115

Table 75: ARL/VLAN Access Registers (Page 05h) ..........................................................................................115

Table 76: ARL Read/Write Control Register (Page 05h: Address 00h) ...........................................................116

Table 77: MAC Address Index Register (Page 05h: Address 02h–07h) ..........................................................117

Table 78: VID Index Register (Page 05h: Address 08h–09h) ..........................................................................117

Table 79: ARL MAC/VID Entry 0 Register (Page 05h: Address 10h–17h) .......................................................117

Table 80: ARL FWD Entry 0 Register (Page 05h: Address 18h–1Bh)...............................................................118

Table 81: ARL MAC/VID Entry 1 Register (Page 05h: Address 20h–27h) .......................................................119

Table 82: ARL FWD Entry 1 Register (Page 05h: Address 28h–2Bh)...............................................................119

Table 83: ARL Search Control Register (Page 05h: Address 30h) ...................................................................120

Table 84: ARL Search Address Register (Page 05h: Address 31h–32h) ..........................................................121

Table 85: ARL Search MAC/VID Result Register 0 (Page 05h: Address 33h–3Ah) ..........................................121

Table 86: ARL Search Result Register 0 (Page 05h: Address 3Bh–3Eh) ..........................................................121

Table 87: ARL Search MAC/VID Result Register 1 (Page 05h: Address 40h–47h) ..........................................122

Table 88: ARL Search Result Register 1 (Page 05h: Address 48h–4Bh) ..........................................................122

Table 89: VLAN Table Read/Write Control Register (Page 05h: Address 60h)...............................................124

Table 90: VLAN Table Address Index Register (Page 05h: Address 61h–62h)................................................124

Table 91: VLAN Table Entry Register (Page 05h: Address 63h–6Ah)..............................................................124

Table 92: Flow Control Registers (Page 0Ah) .................................................................................................125

Table 93: Internal SerDes Registers Page Descriptions 10h–1Fh ...................................................................129

Table 94: Internal SerDes Registers Page 10h–1Fh ........................................................................................129

Table 95: MII Control (Page 10h–1Fh: Address 00h–01h)..............................................................................131

Table 96: MII Status (Page 10h–1Fh: Address 02h–03h)................................................................................132

Table 97: Auto-Negotiation Advertisement (Page 10h–1Fh: Address 08h–09h) ...........................................133

Table 98: Auto-Negotiation Link Partner Ability (Page 10h–1Fh: Address 0Ah–0Bh) ....................................134

Table 99: Auto-Negotiation Expansion (Page 10h–1Fh: Address 0Ch–0Dh) ..................................................135

Table 100: Extended Status (Page 10h–1Fh: Address 1Eh–1Fh) ....................................................................135

Table 101: SerDes/SGMII Control1 (Page 10h–1Fh: Address 20h–21h, Block 0) ...........................................136

Table 102: Analog Transmit Register (Page 10h ~ 1Fh: Address 20h ~ 21h, Block 1).....................................138

Table 103: SerDes/SGMII Control 2 (Page 10h–1Fh: Address 22h–23h)........................................................138

Table 104: SerDes/SGMII Control 3 (Page 10h–1Fh: Address 24h–25h)........................................................139

Table 105: SerDes/SGMII Status 1 (Page 10h–1Fh: Address 28h–29h)..........................................................140

Table 106: SerDes/SGMII Status 2 (Page 10h–1Fh: Address 2Ah–2Bh) .........................................................141

Table 107: SerDes/SGMII Status 3 (Page 10h–1Fh: Address 2Ch–2Dh) .........................................................142

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