CML Microcircuits CMX981：高级数字无线电基带处理器

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"Cmx981芯片手册，包含CML Microcircuits的CMX981先进数字无线电基带处理器的详细技术规格和功能描述。" CMX981是CML Microsystems公司生产的一款高性能的数字无线电基带处理器，专为便携式通信终端设计，具有低功耗和多种功能集成的特点。这款芯片在无线通信领域，特别是TETRA（Terrestrial Trunked Radio）系统中有着广泛的应用。主要特性： 1. **可编程数字发射(Tx)和接收(Rx)滤波器**：CMX981允许用户根据特定通信标准或需求调整发射和接收的数字滤波参数，以优化信号质量。 2. **π/4 DQPSK和其他调制方式**：支持π/4差分正交相移键控（DQPSK）调制，同时也能处理其他类型的调制方式，适应多样的通信标准。 3. **高性能编解码器**：内置高质量的音频编解码器，确保音频信号的高保真传输。 4. **全双工操作**：能够同时进行数据的发送和接收，实现双向通信。 5. **接收端：2个16位Σ-Δ型ADC**：用于将模拟射频信号转换为数字信号，提供高精度的接收性能。 6. **C-BUS和3个快速串行总线接口**：用于与其他设备的高速数据交换和系统扩展。 7. **发射端：2个14位Σ-Δ型DAC**：用于将数字信号转换为模拟信号，驱动发射电路。 8. **辅助功能：6个10位ADC和4个10位DAC**：用于额外的信号采集和生成，增强系统的多功能性。 9. **130mW扬声器放大器（8Ω负载）和16.5mW耳机放大器（32Ω负载）**：内置音频放大器，适用于不同类型的音频输出设备。 10. **2.5V电源供应，3.3V兼容I/O**：供电灵活，兼容多种系统电压标准。在系统架构上，CMX981包括了RRC滤波器、π/4 DQPSK解调器、信道解码器、TDMA帧格式化等关键模块，用于处理TETRA系统的信道编码和时分复用。此外，还集成了本地振荡器、带通滤波器、射频放大器和中频放大器等，实现了完整的发射和接收路径。 CMX981在TETRA接收器中，通过ADC对射频信号进行采样，然后经过RRC滤波和90°解调，再通过通道解码器还原出原始数据。在发射路径中， DAC将数字信号转换成模拟信号，经过π/4 DQPSK调制器、线性功率放大器，最终由RF调制器生成射频信号。总结，CMX981芯片是一款高度集成的通信处理器，具备强大的数字信号处理能力和灵活性，适用于需要高性能音频处理和高效无线通信的便携式设备，特别是在TETRA通信系统中的应用。

Advanced Digital Radio Baseband Processor CMX981

The data RAMs store the filter input data samples and operate upon these values to provide the

general FIR transfer function:

n=FL

y(k) = Σ A

(n-k)

where: FL is the filter tap length,

n=1

is the nth filter coefficient,

(n-k)

is the data sample supplied to the

filter n-k samples previously

When a filter is deactivated, coefficient RAMs retain their state, while the data RAMs are reset to

zero. This ensures that the filters start from a quiescent state and prevents filter "memory" from a

previous data frame. Asserting the N_RESET pin will cause all programmable filter coefficients to

return to default values. Alternatively, the Tx and Rx path filter coefficients may be reset

independently from each other by use of a control bit. The data RAMs, unlike the coefficient

RAMs, are not directly accessible to the user.

To overwrite the default coefficients, the user should first ensure that the Rx and/or Tx path is

inactive as appropriate and that the clocks are not stopped for that channel. Bit 0 in the

ConfigCtrl2 register must then be asserted. Setting this bit high resets the coefficient pointer to

the first coefficient. The most significant bits (eight for the Rx filters, four for the Tx filters) must

then be written to the appropriate coefficient address ($19, $1B, $1D or $1F). Writing the eight

least significant bits to the appropriate coefficient address ($18, $1A, $1C or $1E) will increment

the coefficient pointer to the next location. This process is repeated until all 63 (40 for the 79-tap

filter) locations have been programmed. To program the next filter, bit 0 in the ConfigCtrl2

All filters, except the 79-tap filter, allow access to the complete coefficient set, although the

default values are symmetrical about (FL+1)/2. This will enable users to realise non-symmetrical

filter functions should this be required.

All filters can be effectively bypassed by setting any single coefficient to unity (2

-1 in the Tx and

-1 in Rx) and all others to zero. The chosen positions of the "unity" coefficient will vary the

internal group delay, thus this feature should be used with care. For example, the Tx ramping

feature has a built in delay that defaults to the expected group delay for the Tx filter path. Ramp

delay may be varied, if necessary, by use of the RampCtrl register. The default group delay can

be retained by choosing the central coefficient as "unity". The 79-tap filter has only one half of the

coefficient RAM available, so can only implement symmetrical (linear phase) filter responses.

Thus, when accessing this filter, only locations A1-A40 are valid. In addition, to bypass this filter,

the central coefficient (A40) should be chosen as "unity" since this is the only unique coefficient.

5.2 Programmable Sample Rates

The sample rates of the Tx, Rx and Codec sections can be independently programmed by the

ClkDiv1 and ClkDiv2 registers. The values in these registers determine the MCLK divide ratio

that is used to generate the sample clock for each section. The divide ratios are 16 times the

default value (for TETRA) for the Tx and Rx paths is 4 (divide by 64), giving a sample rate of

144kHz and a symbol rate of 18kHz with a 9.216MHz crystal. The default value for the Codec is 9

(divide by 1152), giving a sample rate of 8kHz with a 9.216MHz crystal.

Advanced Digital Radio Baseband Processor CMX981

5.3 Tx Data Path

5.3.1 FIFO

Symbol data is written to a 4-word deep FIFO. The status of the FIFO can be monitored by the

Status1 register. This register can be used to issue an interrupt once a certain number of full or

empty locations exist within the FIFO. When the serial clock stop mode is enabled, writing data to

the FIFO will stop the serial clock once the FIFO is full. Words written to the FIFO can contain

either one or four symbols to be transmitted. Absolute constellation positions can also be written,

by bypassing the symbol modulator.

5.3.2 Modulator

This takes the 2-bit symbols, performs a Gray code conversion and uses a recursive adder to

generate a 3-bit code representing the eight possible phase states. A look up table provides the

digitally encoded I and Q values for each phase state.

5.3.3 Filters

Digital filtering is applied to the data by two FIR filters. The first has 79 taps and provides stop

band rejection and sampling correction. This filter takes data from the modulator at the symbol

rate (18kHz for TETRA) and interpolates by 8 to the sample rate (144kHz for TETRA). The

CMX981 has a mode that allows data to be written directly to this filter at either rate. The second

filter has 63 taps and provides the primary Root Raised Cosine (RRC) shaping with a roll-off

factor (α) of 0.35. These filters contain default coefficients at power up, but can be overwritten via

the serial interface.

5.3.4 Gain Control

The amplitude of each channel can be adjusted independently. The gain multiplier provides a

resolution of 11 bits; i.e. the gain is adjustable in steps of 1/2048 of the maximum level. Additional

logic allows a mode of operation that will enable ramping up to the set signal level, stay at this

value while instructed by the user, then ramp down to zero.

5.3.5 Phase Pre-distortion

A further feature allows the user to compensate for non-orthogonal carrier phase in the external

quadrature modulator by adding a programmable fraction of up to 1/8 of the filtered I and Q

channel signals to each other immediately prior to the DAC input.

5.3.6 Offset Adjustment

Offset registers allow any offsets introduced in the analogue sections of the transmit path to be

corrected digitally via the serial interface. The offset adjust is independently applied to each of the

I and Q channel. The adjustment range is plus and minus full scale. Thus care must be exercised

by the user to avoid excessive offsets being applied to the sigma-delta DAC.

5.3.7 Output Ramping

A facility is provided to allow ramping of the outputs in two modes. When enabled by the user, the

signal from the gain multiplier stage is multiplied by an envelope value. This value increments or

decrements at a rate programmed by the user. The ramping envelope can be selected by the

user to be linear or sigmoidal. A sigmoidal ramp will minimise spectrum spread while fast ramping

is in progress.

5.3.8 Sigma-Delta D-A Converters and Reconstruction Filters

The converters are designed to have low distortion and >80dB dynamic range. These 2nd order

converters operate at a frequency of 128x symbol rate so as to over-sample the data at their

inputs a further 16 times. The reconstruction filters are 3rd order, switched capacitor, low pass

filters designed to work in conjunction with an external RC.

Advanced Digital Radio Baseband Processor CMX981

5.4 Rx Data Path

5.4.1 Anti-Alias Filtering and Sigma-Delta A-D Converters

The sampling frequency of the Sigma-Delta A-D is 128x symbol rate. The high over-sampling rate

relaxes the design requirements on the anti-alias filter. However, to achieve optimum

performance, the anti-alias filter must reject the sampling frequency to about -110dB, of which at

least 30dB must be provided externally. Additionally, in order to ease the complexity of the

subsequent digital filters, there is a further requirement that the external anti-alias filter suppress

8x symbol rate to about -13dB. The on-chip anti-alias filter can be by-passed and powered down,

although external anti-aliasing must then be provided. The fourth-order Sigma-Delta A-D

converters are designed to have low distortion and >90dB dynamic range. The baseband I and Q

channels must be provided as differential signal; this minimises in-band pick up both on and off

the chip.

Both I and Q Sigma-Delta converters produce a single bit output sampled at MCLK/4. This data is

passed to a non-programmable decimation FIR filter, which is sampled at MCLK/4 and gives

sufficient rejection at 8x symbol rate (MCLK/64) to permit decimation to that frequency. Note that

around -30dB is provided by the primary anti-alias filters.

5.4.2 Rx FIR Filters

Digital filtering is applied to the data from the Sigma-Delta A-D converter decimation filter by two

63-tap FIR filters in cascade. The default coefficients are set to give a RRC response with α of

0.35. The first filter is used to enhance stop-band rejection, while the second filter provides the

primary shaping requirement for RRC response.

5.4.3 I and Q Channel Gain

Programmable gain modules are provided in both I and Q channels. These blocks allow the user

to adjust the dynamic range of the received data within the digital filters, thus optimising the filter

signal to noise performance for a range of levels at the Rx input pins. In the receive section the

gain multiplier sign bit is user accessible, therefore phase inversion in each channel is possible by

programming negative numbers into the gain registers.

The two channels are independently programmable. This enables differential gain corrections to

be made within the digital domain.

5.4.4 Offset Registers

System generated offsets may be removed by control of the offset register via the serial interface.

5.5 Auxiliary Circuits

5.5.1 10-bit DACs

Four 10-bit DACs are provided to assist in a variety of control functions. The DACs are designed

to provide an output as a proportion of the supply voltage, depending on the digital input. They

are monotonic with an absolute accuracy of better than 1%. Control and data for these come via

the serial interface.

5.5.2 10-bit ADC

A 10-bit ADC is provided to assist in a variety of measurement and control functions. The ADC

includes an internal sample and hold circuit and is designed to produce a digital output

proportional to the input voltage, full scale being the positive supply. It is monotonic with an

absolute accuracy of about 1%. An input multiplexer allows the input to be selected from one of

six sources. Control and digital data output is via the serial interface.

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