瑞萨72T36135ML5BB FIFO存储器规格：海量36位配置与高级特性

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本文档是关于C1547702 FIFO存储器的规格书，由日本瑞萨(Renesas)公司生产，型号为72T36135ML5BB。该存储器是TeraSync系列的一部分，专为高速应用设计，支持18位的高数据传输速率。以下主要知识点概述： 1. **产品概述**: - 发布日期：2016年5月 - 版本：DSC-6723/5 - 版权声明：所有权利保留，产品规格可能随时更改。 2. **产品特性**: - **容量与组织**： - 提供了业界最大的FIFO内存组织，拥有524,288个36位单元，总计18M比特。 - **高速性能**： - 最大工作频率可达200MHz，适用于对速度有较高要求的应用。 - **兼容性**： - 与9Mbit IDT72T36125 TeraSync设备功能和引脚兼容，便于升级或替换。 3. **接口选项**： - 用户可选择HSTL/LVTTL输入和/或输出，提供灵活性。 - 支持异步读写端口时间配置，适应不同的系统架构。 4. **控制功能**： - **Mark & Retransmit**：允许读取时重传已标记的数据位置，提高数据可靠性。 - **Chip Select信号**： - Write Chip Select (WCS) 输入可以禁用写入端口，提供数据保护。 - Read Chip Select (RCS) 同步于RCLK，确保数据同步。 5. **标志管理**： - 内置几乎空(ALE)和几乎满(AFE)标志，每个标志可以设置为预选的八个偏移量之一，提供灵活的空闲检测。 6. **可编程性**： - 除了以上特性外，该FIFO存储器还具有程序可配置的标志，用户可以根据需求定制操作行为。 C1547702 FIFO存储器是一款高性能、大容量、灵活配置的接口组件，适用于工业和商业环境中的高速数据传输应用，提供了丰富的功能以满足不同场景的需求。在设计系统时，开发者应仔细考虑这些特性以充分利用其优势。

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T36135M 2.5V 18M-BIT TeraSync

™™

™ 36-BIT FIFO

524,288 x 36

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)

Symbol Parameter Min. Max. Unit

ILI Input Leakage Current –10 10 μA

ILO Output Leakage Current –10 10 μA

(5)

Output Logic “1” Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) VDDQ -0.4 — V

IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) VDDQ -0.4 — V

IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL) VDDQ -0.4 — V

OL Output Logic “0” Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) — 0.4V V

OL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) — 0.4V V

IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL) — 0.4V V

ICC1

(1,2)

Active VCC Current (VCC = 2.5V) I/O = LVTTL — 120 mA

I/O = HSTL — 180 mA

I/O = eHSTL — 180 mA

ICC2

(1)

Standby VCC Current (VCC = 2.5V) I/O = LVTTL — 40 mA

I/O = HSTL — 140 mA

I/O = eHSTL — 140 mA

NOTES:

1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.

2. For the IDT72T36135M, typical ICC1 calculation (with data outputs in Low-Impedance):

3. For all devices, typical IDDQ calculation: with data outputs in High-Impedance: IDDQ (mA) = 0.15 x fs, fs = WCLK = RCLK frequency (in MHz)

with data outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x N)/2000

fs = WCLK = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, CL = capacitive load (pf), tA = 25°C,

N = Number of outputs switching.

4. Total Power consumed: PT = (VCC x ICC) + VDDQ x IDDQ).

5. Outputs are not 3.3V tolerant.

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T36135M 2.5V 18M-BIT TeraSync

™™

™ 36-BIT FIFO

524,288 x 36

AC ELECTRICAL CHARACTERISTICS

(1)

— SYNCHRONOUS TIMING

(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Pulse widths less than minimum values are not allowed.

3. Values guaranteed by design, not currently tested.

4. Industrial temperature range product for 6ns speed grade is available as a standard device. All other speed grades are available by special order.

Commercial Com’l & Ind’l

IDT72T36135ML5 IDT72T36135ML6

Symbol Parameter Min. Max. Min. Max. Unit

fC Clock Cycle Frequency (Synchronous) — 200 — 166 MHz

tA Data Access Time 0.6 3.6 0.6 3.8 ns

tCLK Clock Cycle Time 5 — 6 — ns

tCLKH Clock High Time 2.5 — 3.0 — ns

tCLKL Clock Low Time 2.5 — 3.0 — ns

tDS Data Setup Time 1.5 — 2.0 — ns

tDH Data Hold Time 0.5 — 0.5 — ns

tENS Enable Setup Time 1.5 — 2.0 — ns

tENH Enable Hold Time 0.5 — 0.5 — ns

tLDS Load Setup Time 1.5 — 2.0 — ns

tLDH Load Hold Time 0.5 — 0.5 — ns

tWCSS WCS setup time 1.5 — 2.0 — ns

tWCSH WCS hold time 0.5 — 0.5 — ns

fS Clock Cycle Frequency (SCLK) — 10 — 10 MHz

tSCLK Serial Clock Cycle 100 — 100 — ns

tSCKH Serial Clock High 45 — 45 — ns

tSCKL Serial Clock Low 45 — 45 — ns

tSDS Serial Data In Setup 15 — 15 — ns

tSDH Serial Data In Hold 5 — 5 — ns

tSENS Serial Enable Setup 5 — 5 — ns

tSENH Serial Enable Hold 5 — 5 — ns

tRS Reset Pulse Width

(3)

10 — 10 — ns

tRSS Reset Setup Time 15 — 15 — ns

tHRSS HSTL Reset Setup Time 4 — 4 —

tRSR Reset Recovery Time 10 — 10 — ns

tRSF Reset to Flag and Output Time — 15 — 15 ns

tWFF Write Clock to FF[1:2] or IR[1:2] — 3.6 — 3.7 ns

tREF Read Clock to EF[1:2] or OR[1:2] — 3.6 — 3.7 ns

tPAFS Write Clock to Synchronous PAF[1:2] — 3.6 — 3.7 ns

tPAES Read Clock to Synchronous PAE[1:2] — 3.6 — 3.7 ns

tRCSLZ RCLK to Active from High-Z

(3)

— 3.6 — 3.7 ns

tRCSHZ RCLK to High-Z

(3)

— 3.6 — 3.7 ns

tSKEW1 Skew time between RCLK and WCLK for EF[1:2] and FF[1:2] —4 — 5ns

tSKEW2 Skew time between RCLK and WCLK for PAE[1:2] and PAF[1:2] —5 — 6ns

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