AT89C52单片机：8K Flash内存的微控制器

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"AT89C52是一款由Atmel公司制造的8位低功耗、高性能CMOS微控制器，内含8KB可编程并可擦除的Flash只读存储器(PEROM)。该器件采用Atmel的高密度非易失性内存技术，兼容标准的80C51和80C52指令集和引脚布局。其内部的Flash功能支持在系统编程或通过传统的非易失性内存编程器进行程序更新。AT89C52集成了一个多功能的8位CPU和Flash芯片，是许多嵌入式控制应用的经济高效解决方案。" AT89C52的主要特点和功能包括： 1. **兼容性**：与MCS-51产品系列兼容，这意味着它遵循80C51和80C52微处理器的指令集和硬件接口。 2. **内存**：内置8KB的Flash内存，允许程序在系统内进行多次（至少1,000次）写入/擦除操作，提供灵活的程序更新能力。 3. **操作频率**：支持完全静态操作，工作频率范围从0Hz到24MHz，适应各种速度需求。 4. **程序内存锁定**：具备三级程序内存锁功能，可以保护代码不被非法访问或修改。 5. **内部RAM**：配备256x8位的内部随机存取内存（RAM），用于存储数据和运行时的工作变量。 6. **输入/输出端口**：提供32条可编程的输入/输出线路，可以灵活配置为数字输入或输出。 7. **计数器/定时器**：包含三个16位定时器/计数器，可用于定时、计数、捕获和比较等任务。 8. **中断源**：有八个中断源，增强系统对突发事件的响应能力。 9. **串行通信**：内置可编程串行通道，支持UART（通用异步收发传输器）协议，方便与其他设备进行串行通信。 10. **低功耗模式**：提供低功耗空闲和电源下降模式，有助于在不影响系统性能的情况下降低能耗。 11. **应用领域**：广泛应用于嵌入式控制系统，如家用电器、汽车电子、工业自动化、仪器仪表等领域。需要注意的是，尽管AT89C52是一款功能强大的微控制器，但已不再推荐用于新设计，可能是因为更现代的替代品具有更高的性能、更多的内存或更先进的特性。在选择微控制器时，应考虑其兼容性、性能、功耗以及未来技术支持等因素。

AT89C52

Special Function Registers

A map of the on-chip memory area called the Special Func-

tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc-

cupied addresses may not be implemented on the chip.

Read accesses to these addresses will in general return

random data, and write accesses will have an indetermi-

nate effect.

User software should not write 1s to these unlisted loca-

tions, since they may be used in future products to invoke

new features. In that case, the reset or inactive values of

the new bits will always be 0.

Timer 2 Registers Control and status bits are contained in

registers T2CON (shown in Table 2) and T2MOD (shown in

Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L)

are the Capture/Reload registers for Timer 2 in 16-bit cap-

ture mode or 16-bit auto-reload mode.

Interrupt Registers The individual interrupt enable bits are

in the IE register. Two priorities can be set for each of the

six interrupt sources in the IP register.r

Data Memory

The AT89C52 implements 256 bytes of on-chip RAM. The

upper 128 bytes occupy a parallel address space to the

Special Function Registers. That means the upper 128

bytes have the same addresses as the SFR space but are

physically separate from SFR space.

When an instruction accesses an internal location above

address 7FH, the address mode used in the instruction

specifies whether the CPU accesses the upper 128 bytes

of RAM or the SFR space. Instructions that use direct

addressing access SFR space.

For example, the following direct addressing instruction

accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Table 2. T2CON – Timer/Counter 2 Control Registe

T2CON Address = 0C8H Reset Value = 0000 0000B

Bit Addressable

Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2

CP/RL2

76543210

Symbol Function

TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either

RCLK = 1 or TCLK = 1.

EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and

EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt

routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode

(DCEN = 1).

RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial

port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial

port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX

if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.

C/T2

Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge

triggered).

CP/RL2

Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2

= 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2

= 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

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