STM32F103T8U6R：高性能ARM Cortex-M3微控制器详解

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STM32F103是一款由STMicroelectronics公司生产的高性能32位ARM Cortex-M3架构微控制器，特别适用于中密度应用需求。这款MCU具有显著的特性，如高速性能，最高工作频率可达72MHz，拥有1.25 DMIPS/MHz（Dhrystone 2.1）的运算能力，即使在等待状态时也能保持高效执行。它搭载了64或128 KB的Flash存储器，以及20 KB的SRAM，满足了程序存储和数据处理的需求。在供电和时钟管理方面，STM32F103支持2.0到3.6伏的应用电压和I/O接口，具备上电复位(POR)、掉电复位(PDR)和可编程电压检测(PVD)功能。内置的时钟选项包括4至16 MHz外部晶体振荡器、8 MHz工厂预校准的内部RC振荡器和40 kHz内部RC振荡器，以及用于CPU时钟的锁相环 PLL。此外，还有一个32 kHz的实时时钟(RTC)振荡器，支持精确的时间管理和校准。低功耗是这款MCU的另一大亮点，它提供了睡眠、停机和待机模式，有助于节省电池寿命。特别地，还配备了VBAT电源，用于支持RTC和备份寄存器在低功耗状态下工作。集成的硬件包括两个12位、1 µs分辨率的模拟-数字转换器(ADC)，最多支持16通道，支持双采样保持功能，可用于测量电压和温度。在I/O和外设方面，STM32F103拥有强大的DMA控制器，可以控制多达7个通道，支持多个定时器、ADC、SPI、I2C和USART接口，提供灵活的外设配置选项。该MCU拥有高达80个快速输入/输出端口，可以根据需要映射到16个外部引脚上，非常适合各种外围设备的连接。 STM32F103T8U6R是一款集成了高性能处理器、丰富的存储资源、多样化的时钟和电源管理、低功耗特性和广泛的外设接口的嵌入式系统解决方案，适用于需要高性能和能效比的多种应用场景，例如物联网、工业自动化和消费电子等领域。对于开发者来说，熟悉并掌握这款芯片的功能和使用方法将大大提高项目开发效率。

Description STM32F103x8, STM32F103xB

16/96 Doc ID 13587 Rev 12

in reset mode when V

is below a specified threshold, V

POR/PDR

, without the need for an

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be

generated when V

DDA

drops below the V

PVD

threshold and/or when V

DDA

is higher

than the V

PVD

threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

Refer to Table 11: Embedded reset and power control block characteristics for the values of

POR/PDR

and V

PVD

2.3.11 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in the nominal regulation mode (Run)

● LPR is used in the Stop mode

● Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high

impedance output.

2.3.12 Low-power modes

The STM32F103xx performance line supports three low-power modes to achieve the best

compromise between low power consumption, short startup time and available wakeup

sources:

● Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

● Stop mode

The Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB

wakeup.

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

STM32F103x8, STM32F103xB Description

Doc ID 13587 Rev 12 17/96

2.3.13 DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose and

advanced-control timers TIMx and ADC.

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V

BAT

pin. The backup registers are ten 16-bit

registers used to store 20 bytes of user application data when V

power is not present.

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the

internal low-power RC oscillator or the high-speed external clock divided by 128. The

internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using

an external 512 Hz output to compensate for any natural crystal deviation. The RTC features

a 32-bit programmable counter for long-term measurement using the Compare register to

generate an alarm. A 20-bit prescaler is used for the time base clock and is by default

configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.15 Timers and watchdogs

The medium-density STM32F103xx performance line devices include an advanced-control

timer, three general-purpose timers, two watchdog timers and a SysTick timer.

Table 4 compares the features of the advanced-control and general-purpose timers.

Table 4. Timer feature comparison

Timer

Counter

resolution

Counter

type

Prescaler

factor

DMA request

generation

Capture/compare

channels

Complementary

outputs

TIM1 16-bit

Up,

down,

up/down

Any integer

between 1

and 65536

Ye s 4 Ye s

TIM2,

TIM3,

TIM4

16-bit

Up,

down,

up/down

Any integer

between 1

and 65536

Ye s 4 N o

Description STM32F103x8, STM32F103xB

18/96 Doc ID 13587 Rev 12

Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6

channels. It has complementary PWM outputs with programmable inserted dead-times. It

can also be seen as a complete general-purpose timer. The 4 independent channels can be

used for

● Input capture

● Output compare

● PWM generation (edge- or center-aligned modes)

● One-pulse mode output

If configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. If

configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs

disabled to turn off any power switch driven by these outputs.

Many features are shared with those of the general-purpose TIM timers which have the

same architecture. The advanced-control timer can therefore work together with the TIM

timers via the Timer Link feature for synchronization or event chaining.

General-purpose timers (TIMx)

There are up to three synchronizable general-purpose timers embedded in the

STM32F103xx performance line devices. These timers are based on a 16-bit auto-reload

up/down counter, a 16-bit prescaler and feature 4 independent channels each for input

capture/output compare, PWM or one-pulse mode output. This gives up to 12 input

captures/output compares/PWMs on the largest packages.

The general-purpose timers can work together with the advanced-control timer via the Timer

Link feature for synchronization or event chaining. Their counter can be frozen in debug

mode. Any of the general-purpose timers can be used to generate PWM outputs. They all

have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently of the

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free-running timer for application timeout

management. It is hardware- or software-configurable through the option bytes. The counter

can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from the

main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

STM32F103x8, STM32F103xB Description

Doc ID 13587 Rev 12 19/96

SysTick timer

This timer is dedicated for OS, but could also be used as a standard downcounter. It

features:

● A 24-bit downcounter

● Autoreload capability

● Maskable system interrupt generation when the counter reaches 0

● Programmable clock source

2.3.16 I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support

standard and fast modes.

They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master

mode. A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SM Bus 2.0/PM Bus.

2.3.17 Universal synchronous/asynchronous receiver transmitter (USART)

One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The

other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware

management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816

compliant and have LIN Master/Slave capability.

All USART interfaces can be served by the DMA controller.

2.3.18 Serial peripheral interface (SPI)

Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-

duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC modes.

Both SPIs can be served by the DMA controller.

2.3.19 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It

can receive and transmit standard frames with 11-bit identifiers as well as extended frames

with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

2.3.20 Universal serial bus (USB)

The STM32F103xx performance line embeds a USB device peripheral compatible with the

USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function

interface. It has software-configurable endpoint setting and suspend/resume support. The

dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use

a HSE crystal oscillator).

Description STM32F103x8, STM32F103xB

20/96 Doc ID 13587 Rev 12

2.3.21 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-

capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

I/Os on APB2 with up to 18 MHz toggling speed

2.3.22 ADC (analog-to-digital converter)

Two 12-bit analog-to-digital converters are embedded into STM32F103xx performance line

devices and each ADC shares up to 16 external channels, performing conversions in single-

shot or scan modes. In scan mode, automatic conversion is performed on a selected group

of analog inputs.

Additional logic functions embedded in the ADC interface allow:

● Simultaneous sample and hold

● Interleaved sample and hold

● Single shunt

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all selected channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) and the advanced-control timer

(TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA

trigger respectively, to allow the application to synchronize A/D conversion and timers.

2.3.23 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The

conversion range is between 2 V < V

DDA

< 3.6 V. The temperature sensor is internally

connected to the ADC12_IN16 input channel which is used to convert the sensor output

voltage into a digital value.

2.3.24 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a

specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

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