MIPS32指令集手册：程序员指南

需积分: 9 121 浏览量更新于2024-07-18 收藏 2.28MB PDF 举报

"MIPS32指令集手册是MIPS架构程序员第二卷A部分的官方文档，详细介绍了MIPS32指令集。该手册由Imagination Technologies Ltd.及其关联公司版权所有，版本为6.06，发布日期为2016年12月15日。文档中包含了对MIPS32架构的专有信息，可能会随时更改，且无任何保修。" 正文: MIPS（Microprocessor without Interlocked Pipeline Stages，无锁流水线阶段微处理器）是一种精简指令集计算机（RISC）架构，广泛用于嵌入式系统和教育领域。MIPS32是MIPS架构的一个32位变种，它提供了一套高效、简洁的指令集，旨在满足各种应用的需求。本书《MIPS32指令集手册》是针对程序员的指南，旨在帮助开发者理解和使用MIPS32指令集。手册包含了关于MIPS32指令集的详细描述，包括每个指令的功能、操作和使用场景。文档的结构严谨，采用了特定的排版规则来增强可读性。 1.1章节介绍了文档中的排版约定。其中： - **斜体文本**通常用来表示新的术语或概念。 - **粗体文本**用来突出重要的信息或标题。 - **仿宋文本**通常用于表示代码、指令名或特定的编程元素。 1.2章节则详细解释了在MIPS指令集中遇到的三个关键状态： - **UNPREDICTABLE** 指令的行为不能被准确预测，可能因实现而异。 - **UNDEFINED** 表示指令没有定义的行为，执行时可能会导致未定义的后果。 - **UNSTABLE** 是一个相对少见的状态，可能表示某些条件下的行为不稳定或不确定。 1.3章节讨论了伪代码表示法中的特殊符号，这些符号在描述指令操作时起到关键作用，帮助开发者理解指令执行逻辑。 1.4章节介绍了寄存器字段的记号法，这对于理解指令如何处理和存储数据至关重要，因为MIPS指令集使用寄存器作为主要的数据交互方式。手册的其余部分会详细阐述MIPS32指令集中的各个指令，包括算术运算、逻辑运算、分支、内存访问、浮点运算（如果支持FPU）、向量处理等。此外，它还会涵盖异常、中断、寻址模式以及程序控制和状态寄存器的使用。通过深入学习这本书，开发者可以编写高效的MIPS32汇编代码，充分利用硬件的性能。

1.3 Special Symbols in Pseudocode Notation

The MIPS32® Instruction Set Manual, Revision 6.06 6

CPR[z,x,s] Coprocessor unit z, general register x, select s

CP2CPR[x] Coprocessor unit 2, general register x

CCR[z,x] Coprocessor unit z, control register x

CP2CCR[x] Coprocessor unit 2, control register x

COC[z] Coprocessor unit z condition signal

Xlat[x] Translation of the MIPS16e GPR number x into the corresponding 32-bit GPR number

BigEndianMem Endian mode as configured at chip reset (0 Little-Endian, 1  Big-Endian). Specifies the endianness of

the memory interface (see LoadMemory and StoreMemory pseudocode function descriptions) and the endi-

anness of Kernel and Supervisor mode execution.

BigEndianCPU The endianness for load and store instructions (0  Little-Endian, 1  Big-Endian). In User mode, this

endianness may be switched by setting the RE bit in the Status register. Thus, BigEndianCPU may be com-

puted as (BigEndianMem XOR ReverseEndian).

ReverseEndian Signal to reverse the endianness of load and store instructions. This feature is available in User mode only,

and is implemented by setting the RE bit of the Status register. Thus, ReverseEndian may be computed as

(SR

and User mode).

LLbit Bit of virtual state used to specify operation for instructions that provide atomic read-modify-write. LLbit is

set when a linked load occurs and is tested by the conditional store. It is cleared, during other CPU operation,

when a store to the location would no longer be atomic. In particular, it is cleared by exception return instruc-

tions.

I:,

I+n:,

I-n:

This occurs as a prefix to Operation description lines and functions as a label. It indicates the instruction

time during which the pseudocode appears to “execute.” Unless otherwise indicated, all effects of the current

instruction appear to occur during the instruction time of the current instruction. No label is equivalent to a

time label of I. Sometimes effects of an instruction appear to occur either earlier or later — that is, during the

instruction time of another instruction. When this happens, the instruction operation is written in sections

labeled with the instruction time, relative to the current instruction I, in which the effect of that pseudocode

appears to occur. For example, an instruction may have a result that is not available until after the next

instruction. Such an instruction has the portion of the instruction operation description that writes the result

The effect of pseudocode statements for the current instruction labeled I+1 appears to occur “at the same

time” as the effect of pseudocode statements labeled I for the following instruction. Within one pseudocode

sequence, the effects of the statements take place in order. However, between sequences of statements for

different instructions that occur “at the same time,” there is no defined order. Programs must not depend on a

particular order of evaluation between such sections.

PC The Program Counter value. During the instruction time of an instruction, this is the address of the instruc-

tion word. The address of the instruction that occurs during the next instruction time is determined by assign-

ing a value to PC during an instruction time. If no value is assigned to PC during an instruction time by any

pseudocode statement, it is automatically incremented by either 2 (in the case of a 16-bit MIPS16e instruc-

tion) or 4 before the next instruction time. A taken branch assigns the target address to the PC during the

instruction time of the instruction in the branch delay slot.

In the MIPS Architecture, the PC value is only visible indirectly, such as when the processor stores the restart

address into a GPR on a jump-and-link or branch-and-link instruction, or into a Coprocessor 0 register on an

exception. Release 6 adds PC-relative address computation and load instructions. The PC value contains a

full 32-bit address, all of which are significant during a memory reference.

Table 1.1 Symbols Used in Instruction Operation Statements (Continued)

Symbol Meaning

About This Book

7 The MIPS32® Instruction Set Manual, Revision 6.06

1.4 Notation for Register Field Accessibility

In this document, the read/write properties of register fields use the notations shown in Table 1.1.

ISA Mode In processors that implement the MIPS16e Application Specific Extension or the microMIPS base architec-

tures, the ISA Mode is a single-bit register that determines in which mode the processor is executing, as fol-

lows:

In the MIPS Architecture, the ISA Mode value is only visible indirectly, such as when the processor stores a

combined value of the upper bits of PC and the ISA Mode into a GPR on a jump-and-link or branch-and-link

instruction, or into a Coprocessor 0 register on an exception.

PABITS The number of physical address bits implemented is represented by the symbol PABITS. As such, if 36 phys-

ical address bits were implemented, the size of the physical address space would be 2

PABITS

= 2

bytes.

FP32RegistersMode Indicates whether the FPU has 32-bit or 64-bit floating point registers (FPRs). In MIPS32 Release 1, the FPU

has 32, 32-bit FPRs, in which 64-bit data types are stored in even-odd pairs of FPRs. In MIPS64, (and

optionally in MIPS32 Release2 and Release 3) the FPU has 32 64-bit FPRs in which 64-bit data types are

stored in any FPR.

In MIPS32 Release 1 implementations, FP32RegistersMode is always a 0. MIPS64 implementations have a

compatibility mode in which the processor references the FPRs as if it were a MIPS32 implementation. In

such a case FP32RegisterMode is computed from the FR bit in the Status register. If this bit is a 0, the pro-

cessor operates as if it had 32, 32-bit FPRs. If this bit is a 1, the processor operates with 32 64-bit FPRs.

The value of FP32RegistersMode is computed from the FR bit in the Status register.

InstructionInBranchDe-

laySlot

Indicates whether the instruction at the Program Counter address was executed in the delay slot of a branch

or jump. This condition reflects the dynamic state of the instruction, not the static state. That is, the value is

false if a branch or jump occurs to an instruction whose PC immediately follows a branch or jump, but which

is not executed in the delay slot of a branch or jump.

SignalException(excep-

tion, argument)

Causes an exception to be signaled, using the exception parameter as the type of exception and the argument

parameter as an exception-specific argument). Control does not return from this pseudocode function—the

exception is signaled at the point of the call.

Table 1.2 Read/Write Register Field Notation

Read/Write

Notation Hardware Interpretation Software Interpretation

R/W A field in which all bits are readable and writable by software and, potentially, by hardware.

Hardware updates of this field are visible by software read. Software updates of this field are visible by

hardware read.

If the Reset State of this field is ‘‘Undefined’’, either software or hardware must initialize the value before

the first read will return a predictable value. This should not be confused with the formal definition of

UNDEFINED behavior.

Table 1.1 Symbols Used in Instruction Operation Statements (Continued)

Symbol Meaning

Encoding Meaning

0 The processor is executing 32-bit MIPS instructions

1 The processor is executing MIIPS16e or microMIPS

instructions

1.4 Notation for Register Field Accessibility

The MIPS32® Instruction Set Manual, Revision 6.06 8

R A field which is either static or is updated only by

hardware.

If the Reset State of this field is either ‘‘0’’, ‘‘Pre-

set’’, or ‘‘Externally Set’’, hardware initializes this

field to zero or to the appropriate state, respectively,

on powerup. The term ‘‘Preset’’ is used to suggest

that the processor establishes the appropriate state,

whereas the term ‘‘Externally Set’’ is used to sug-

gest that the state is established via an external

source (e.g., personality pins or initialization bit

stream). These terms are suggestions only, and are

not intended to act as a requirement on the imple-

mentation.

If the Reset State of this field is ‘‘Undefined’’, hard-

ware updates this field only under those conditions

specified in the description of the field.

A field to which the value written by software is

ignored by hardware. Software may write any value

to this field without affecting hardware behavior.

Software reads of this field return the last value

updated by hardware.

If the Reset State of this field is ‘‘Undefined’’, soft-

ware reads of this field result in an UNPREDICT-

ABLE value except after a hardware update done

under the conditions specified in the description of

the field.

R0 R0 = reserved, read as zero, ignore writes by soft-

ware.

Hardware ignores software writes to an R0 field.

Neither the occurrence of such writes, nor the val-

ues written, affects hardware behavior.

Hardware always returns 0 to software reads of R0

fields.

The Reset State of an R0 field must always be 0.

If software performs an mtc0 instruction which

writes a non-zero value to an R0 field, the write to

the R0 field will be ignored, but permitted writes to

other fields in the register will not be affected.

Architectural Compatibility: R0 fields are reserved,

and may be used for not-yet-defined purposes in

future revisions of the architecture.

When writing an R0 field, current software should

only write either all 0s, or, preferably, write back the

same value that was read from the field.

Current software should not assume that the value

read from R0 fields is zero, because this may not be

true on future hardware.

Future revisions of the architecture may redefine an

R0 field, but must do so in such a way that software

which is unaware of the new definition and either

writes zeros or writes back the value it has read from

the field will continue to work correctly.

Writing back the same value that was read is guaran-

teed to have no unexpected effects on current or

future hardware behavior. (Except for non-atomicity

of such read-writes.)

Writing zeros to an R0 field may not be preferred

because in the future this may interfere with the oper-

ation of other software which has been updated for

the new field definition.

Table 1.2 Read/Write Register Field Notation (Continued)

Read/Write

Notation Hardware Interpretation Software Interpretation

About This Book

9 The MIPS32® Instruction Set Manual, Revision 6.06

1.5 For More Information

MIPS processor manuals and additional information about MIPS products can be found at http://www.imgtec.com.

For comments or questions on the MIPS32® Architecture or this document, send Email to IMGBA-DocFeed-

back@imgtec.com.

0 Release 6

Release 6 legacy “0” behaves like R0 - read as zero, nonzero writes ignored.

Legacy “0” should not be defined for any new control register fields; R0 should be used instead.

HW returns 0 when read.

HW ignores writes.

Only zero should be written, or, value read from reg-

ister.

pre-Release 6

pre-Release 6 legacy “0” - read as zero, nonzero writes UNDEFINED

A field which hardware does not update, and for

which hardware can assume a zero value.

A field to which the value written by software must

be zero. Software writes of non-zero values to this

field may result in UNDEFINED behavior of the

hardware. Software reads of this field return zero as

long as all previous software writes are zero.

If the Reset State of this field is ‘‘Undefined’’, soft-

ware must write this field with zero before it is guar-

anteed to read as zero.

R/W0 Like R/W, except that writes of non-zero to a R/W0 field are ignored.

E.g. Status.NMI

Hardware may set or clear an R/W0 bit.

Hardware ignores software writes of nonzero to an

R/W0 field. Neither the occurrence of such writes,

nor the values written, affects hardware behavior.

Software writes of 0 to an R/W0 field may have an

effect.

Hardware may return 0 or nonzero to software

reads of an R/W0 bit.

If software performs an mtc0 instruction which

writes a non-zero value to an R/W0 field, the write

to the R/W0 field will be ignored, but permitted

writes to other fields in the register will not be

affected.

Software can only clear an R/W0 bit.

Software writes 0 to an R/W0 field to clear the field.

Software writes nonzero to an R/W0 bit in order to

guarantee that the bit is not affected by the write.

Table 1.2 Read/Write Register Field Notation (Continued)

Read/Write

Notation Hardware Interpretation Software Interpretation

剩余484页未读，继续阅读

chlf99

粉丝: 0
资源: 4

MIPS32指令集手册：程序员指南

"浙大计算机学院：MIPS指令集解析与应用

MIPS32指令集详解

MIPS32指令集详解：编程者指南

MIPS 指令集 The MIPS32 Instruction Set 详细介绍了MIPS指令

mips32 manual

MIPS32® 74KTM Processor Core Family Software User’s Manual

mips vz 1.06 manual 英文版

MIPS指令集

MIPS Open 64 指令集手册 卷二

MIPS Open 64 指令集手册 卷三

最新资源

MIPS Open 64 指令集手册卷二

MIPS Open 64 指令集手册卷三