"FM31xx_r2[1].1芯片资料介绍及预生产产品特性介绍"。

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The document "FM31xx_r2[1].1-芯片资料介绍.pdf" provides an introduction to the FM3104/16/64/256 Integrated Processor Companion with Memory, a product in the pre-production phase of development by Ramtron International Corporation. The characterization of the device is complete and the company does not expect to change the specifications. However, it is stated that Ramtron will issue a Product Change Notice if any specification changes are made. The FM3104/16/64/256 is highlighted for its high integration, which suggests that it combines multiple functions and features into a single chip. This integrated processor companion with memory is designed to offer a comprehensive solution for certain applications or systems. The document does not go into detail about the specific features of the FM3104/16/64/256, but it is likely to include a combination of processing capabilities and memory storage within a single device. The document also provides the contact information for Ramtron International Corporation, including their address at 1850 Ramtron Drive, Colorado Springs, CO 80921, and their phone numbers at (800) 545-FRAM and (719) 481-7000. Additionally, their website www.ramtron.com is provided for further information and inquiries regarding the FM3104/16/64/256 Integrated Processor Companion with Memory. In conclusion, the document "FM31xx_r2[1].1-芯片资料介绍.pdf" introduces the FM3104/16/64/256 Integrated Processor Companion with Memory in the pre-production phase of development by Ramtron International Corporation. The document emphasizes the high integration of the device and provides contact information for further inquiries.

FM3104/16/64/256

Rev 2.1

Dec. 2004 Page 5 of 24

The watchdog timer can also be used to assert the

reset signal (/RST). The watchdog is a free running

programmable timer. The period can be software

programmed from 100 ms to 3 seconds in 100 ms

increments via a 5-bit nonvolatile register. All

programmed settings are minimum values and vary

with temperature according to the operating

specifications. The watchdog has two additional

controls associated with its operation, a watchdog

enable bit (WDE) and timer restart bits (WR). Both

the enable bit must be set and the watchdog must

timeout in order to drive /RST active. If a reset event

occurs, the timer will automatically restart on the

rising edge of the reset pulse. If not enabled, the

watchdog timer runs but has no effect on /RST. Note

that setting the maximum timeout setting (11111b)

disables the counter to save power. The second

control is a nibble that restarts the timer preventing a

reset. The timer should be restarted after changing the

timeout value.

The watchdog timeout value is located in register

0Ah, bits 4-0, and the watchdog enable is bit 7. The

watchdog is restarted by writing the pattern 1010b to

the lower nibble of register 09h. Writing this pattern

will also cause the timer to load new timeout values.

Writing other patterns to this address will not affect

its operation. Note the watchdog timer is free-

running. Prior to enabling it, users should restart the

timer as described above. This assures that the full

timeout period will be set immediately after enabling.

The watchdog is disabled when V

is below V

The following table summarizes the watchdog bits. A

block diagram follows.

Watchdog timeout WDT4-0 0Ah, bits 4-0

Watchdog enable WDE 0Ah, bit 7

Watchdog restart WR3-0 09h, bits 3-0

Figure 3. Watchdog Timer

Manual Reset

The /RST pin is bi-directional and allows the

FM31xx to filter and de-bounce a manual reset

switch. The /RST input detects an external low

condition and responds by driving the /RST signal

low for 100 ms.

Figure 4. Manual Reset

Note that an internal weak pull-up on /RST

eliminates the need for additional external

components.

Reset Flags

In case of a reset condition, a flag will be set to

indicate the source of the reset. A low V

reset or

manual reset is indicated by the POR flag, register

09h bit 6. A watchdog reset is indicated by the WTR

flag, register 09h bit 7. Note that the flags are

internally set in response to reset sources, but they

must be cleared by the user. When the register is

read, it is possible that both flags are set if both have

occurred since the user last cleared them.

Early Power Fail Comparator

An early power fail warning can be provided to the

processor well before V

drops out of spec. The

comparator is used to create a power fail interrupt

(NMI). This can be accomplished by connecting the

PFI pin to the unregulated power supply via a resistor

divider. An application circuit is shown below. The

voltage on the PFI input pin is compared to an

onboard 1.2V reference. When the PFI input voltage

drops below this threshold, the comparator will drive

the CAL/PFO pin to a low state. The comparator has

100 mV (max) of hysteresis to reduce noise

sensitivity, only for a rising PFI signal. For a falling

PFI edge, there is no hysteresis.

Figure 5. Comparator as Early Power-Fail Warning

1.2V ref

Regulator

VDD

FM31xx

To MCU

NMI input

CAL/PFO

PFI

Timebase

Counter

Watchdog

timeout

100 ms

clock

WDE

/RST

WR3-0 = 1010b to restart

FM31xx

Reset

Switch

RST

MCU

Switch

Behavior

RST

FM31xx

drives

100 ms

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