多核处理器时代：计算机体系结构量化研究方法(英文第四版)

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"《计算机体系结构量化研究方法(英文第四版)》是计算机科学领域的一本经典教材，由权威专家撰写，详细介绍了计算机体系结构的设计基础和关键技术。本书全面覆盖了指令集系统结构、流水线技术、指令集并行、多层次存储系统、存储设备、互连网络和多处理器系统等多个核心主题。第四版特别关注了从单核到多核处理器的转变，强调了量化研究方法在计算设计中的应用，并深入探讨了多处理器体系结构的性能、可靠性和可用性等方面。" 在计算机体系结构中，量化研究方法是一种重要的分析和设计工具，它通过数学模型和实验数据来评估和优化系统的性能。这种方法在《计算机体系结构量化研究方法》中被广泛运用，帮助读者理解和预测不同架构决策对系统性能的影响。书中详细阐述了如何利用这种定量方法来衡量和比较不同设计方案的优劣，使读者能够基于实际数据做出明智的设计选择。指令集系统结构（ISA）是计算机硬件与软件之间的接口，书中对其进行了深入讨论，包括指令集的设计原则、指令格式和操作码，以及如何通过ISA设计来影响程序执行效率。流水线技术是提升处理器性能的重要手段，作者详细解释了流水线的工作原理，如分段、数据 hazards 和控制 hazards 的处理，以及如何通过改进流水线设计来减少延迟。指令集并行技术，如超标量、超线程和向量处理，是现代处理器提高并行性的关键。书中介绍了这些技术的实现方式，以及它们在多核环境下的应用。层次化存储系统，包括缓存层次结构，是解决速度与容量之间矛盾的有效策略。书中详细分析了缓存的工作机制、替换策略和缓存一致性问题，这些都是理解存储系统性能的关键。在多处理器系统部分，作者不仅关注性能，还涵盖了多核处理器设计的其他重要方面，如处理器间通信、负载均衡、容错性和可用性。他们讨论了各种互连网络的设计，如总线、交叉开关和交换网络，以及这些网络如何影响多处理器的性能和扩展性。此外，书中还引入了新兴领域的研究，鼓励读者探索计算机架构的前沿趋势。新的练习模式则旨在提高读者的实践能力，通过解决实际问题来深化理论知识的理解。《计算机体系结构量化研究方法(英文第四版)》是一本全面而深入的教材，不仅适合计算机科学专业的学生，也对研究人员和工程技术人员有很高的参考价值，帮助他们在快速发展的多核时代中，掌握计算机体系结构的核心知识和最新进展。

Why We Wrote This Book

Through four editions of this book, our goal has been to describe the basic princi-

ples underlying what will be tomorrow’s technological developments. Our

excitement about the opportunities in computer architecture has not abated, and

we echo what we said about the ﬁeld in the ﬁrst edition: “It is not a dreary science

of paper machines that will never work. No! It’s a discipline of keen intellectual

interest, requiring the balance of marketplace forces to cost-performance-power,

leading to glorious failures and some notable successes.”

Our primary objective in writing our ﬁrst book was to change the way people

learn and think about computer architecture. We feel this goal is still valid and

important. The ﬁeld is changing daily and must be studied with real examples

and measurements on real computers, rather than simply as a collection of deﬁni-

tions and designs that will never need to be realized. We offer an enthusiastic

welcome to anyone who came along with us in the past, as well as to those who

are joining us now. Either way, we can promise the same quantitative approach

to, and analysis of, real systems.

As with earlier versions, we have strived to produce a new edition that will

continue to be as relevant for professional engineers and architects as it is for

those involved in advanced computer architecture and design courses. As much

as its predecessors, this edition aims to demystify computer architecture through

an emphasis on cost-performance-power trade-offs and good engineering design.

We believe that the ﬁeld has continued to mature and move toward the rigorous

quantitative foundation of long-established scientiﬁc and engineering disciplines.

This Edition

The fourth edition of Computer Architecture: A Quantitative Approach may be

the most signiﬁcant since the ﬁrst edition. Shortly before we started this revision,

Intel announced that it was joining IBM and Sun in relying on multiple proces-

sors or cores per chip for high-performance designs. As the ﬁrst ﬁgure in the

book documents, after 16 years of doubling performance every 18 months, sin-

Preface

xvi ■ Preface

gle-processor performance improvement has dropped to modest annual improve-

ments. This fork in the computer architecture road means that for the ﬁrst time in

history, no one is building a much faster sequential processor. If you want your

program to run signiﬁcantly faster, say, to justify the addition of new features,

you’re going to have to parallelize your program.

Hence, after three editions focused primarily on higher performance by

exploiting instruction-level parallelism (ILP), an equal focus of this edition is

thread-level parallelism (TLP) and data-level parallelism (DLP). While earlier

editions had material on TLP and DLP in big multiprocessor servers, now TLP

and DLP are relevant for single-chip multicores. This historic shift led us to

change the order of the chapters: the chapter on multiple processors was the sixth

chapter in the last edition, but is now the fourth chapter of this edition.

The changing technology has also motivated us to move some of the content

from later chapters into the ﬁrst chapter. Because technologists predict much

higher hard and soft error rates as the industry moves to semiconductor processes

with feature sizes 65 nm or smaller, we decided to move the basics of dependabil-

ity from Chapter 7 in the third edition into Chapter 1. As power has become the

dominant factor in determining how much you can place on a chip, we also

beefed up the coverage of power in Chapter 1. Of course, the content and exam-

ples in all chapters were updated, as we discuss below.

In addition to technological sea changes that have shifted the contents of this

edition, we have taken a new approach to the exercises in this edition. It is sur-

prisingly difﬁcult and time-consuming to create interesting, accurate, and unam-

biguous exercises that evenly test the material throughout a chapter. Alas, the

Web has reduced the half-life of exercises to a few months. Rather than working

out an assignment, a student can search the Web to ﬁnd answers not long after a

book is published. Hence, a tremendous amount of hard work quickly becomes

unusable, and instructors are denied the opportunity to test what students have

learned.

To help mitigate this problem, in this edition we are trying two new ideas.

First, we recruited experts from academia and industry on each topic to write the

exercises. This means some of the best people in each ﬁeld are helping us to cre-

ate interesting ways to explore the key concepts in each chapter and test the

reader’s understanding of that material. Second, each group of exercises is orga-

nized around a set of case studies. Our hope is that the quantitative example in

each case study will remain interesting over the years, robust and detailed enough

to allow instructors the opportunity to easily create their own new exercises,

should they choose to do so. Key, however, is that each year we will continue to

release new exercise sets for each of the case studies. These new exercises will

have critical changes in some parameters so that answers to old exercises will no

longer apply.

Another signiﬁcant change is that we followed the lead of the third edition of

Computer Organization and Design (COD) by slimming the text to include the

material that almost all readers will want to see and moving the appendices that

Preface ■ xvii

some will see as optional or as reference material onto a companion CD. There

were many reasons for this change:

1. Students complained about the size of the book, which had expanded from

594 pages in the chapters plus 160 pages of appendices in the ﬁrst edition to

760 chapter pages plus 223 appendix pages in the second edition and then to

883 chapter pages plus 209 pages in the paper appendices and 245 pages in

online appendices. At this rate, the fourth edition would have exceeded 1500

pages (both on paper and online)!

2. Similarly, instructors were concerned about having too much material to

cover in a single course.

3. As was the case for COD, by including a CD with material moved out of the

text, readers could have quick access to all the material, regardless of their

ability to access Elsevier’s Web site. Hence, the current edition’s appendices

will always be available to the reader even after future editions appear.

4. This ﬂexibility allowed us to move review material on pipelining, instruction

sets, and memory hierarchy from the chapters and into Appendices A, B, and

C. The advantage to instructors and readers is that they can go over the review

material much more quickly and then spend more time on the advanced top-

ics in Chapters 2, 3, and 5. It also allowed us to move the discussion of some

topics that are important but are not core course topics into appendices on the

CD. Result: the material is available, but the printed book is shorter. In this

edition we have 6 chapters, none of which is longer than 80 pages, while in

the last edition we had 8 chapters, with the longest chapter weighing in at 127

pages.

5. This package of a slimmer core print text plus a CD is far less expensive to

manufacture than the previous editions, allowing our publisher to signiﬁ-

cantly lower the list price of the book. With this pricing scheme, there is no

need for a separate international student edition for European readers.

Yet another major change from the last edition is that we have moved the

embedded material introduced in the third edition into its own appendix, Appen-

dix D. We felt that the embedded material didn’t always ﬁt with the quantitative

evaluation of the rest of the material, plus it extended the length of many chapters

that were already running long. We believe there are also pedagogic advantages

in having all the embedded information in a single appendix.

This edition continues the tradition of using real-world examples to demon-

strate the ideas, and the “Putting It All Together” sections are brand new; in fact,

some were announced after our book was sent to the printer. The “Putting It All

Together” sections of this edition include the pipeline organizations and memory

hierarchies of the Intel Pentium 4 and AMD Opteron; the Sun T1 (“Niagara”) 8-

processor, 32-thread microprocessor; the latest NetApp Filer; the Internet

Archive cluster; and the IBM Blue Gene/L massively parallel processor.

xviii ■ Preface

Topic Selection and Organization

As before, we have taken a conservative approach to topic selection, for there are

many more interesting ideas in the ﬁeld than can reasonably be covered in a treat-

ment of basic principles. We have steered away from a comprehensive survey of

every architecture a reader might encounter. Instead, our presentation focuses on

core concepts likely to be found in any new machine. The key criterion remains

that of selecting ideas that have been examined and utilized successfully enough

to permit their discussion in quantitative terms.

Our intent has always been to focus on material that is not available in equiva-

lent form from other sources, so we continue to emphasize advanced content

wherever possible. Indeed, there are several systems here whose descriptions

cannot be found in the literature. (Readers interested strictly in a more basic

introduction to computer architecture should read Computer Organization and

Design: The Hardware/Software Interface, third edition.)

An Overview of the Content

Chapter 1 has been beefed up in this edition. It includes formulas for static

power, dynamic power, integrated circuit costs, reliability, and availability. We go

into more depth than prior editions on the use of the geometric mean and the geo-

metric standard deviation to capture the variability of the mean. Our hope is that

these topics can be used through the rest of the book. In addition to the classic

quantitative principles of computer design and performance measurement, the

benchmark section has been upgraded to use the new SPEC2006 suite.

Our view is that the instruction set architecture is playing less of a role today

than in 1990, so we moved this material to Appendix B. It still uses the MIPS64

architecture. For fans of ISAs, Appendix J covers 10 RISC architectures, the

80x86, the DEC VAX, and the IBM 360/370.

Chapters 2 and 3 cover the exploitation of instruction-level parallelism in

high-performance processors, including superscalar execution, branch prediction,

speculation, dynamic scheduling, and the relevant compiler technology. As men-

tioned earlier, Appendix A is a review of pipelining in case you need it. Chapter 3

surveys the limits of ILP. New to this edition is a quantitative evaluation of multi-

threading. Chapter 3 also includes a head-to-head comparison of the AMD Ath-

lon, Intel Pentium 4, Intel Itanium 2, and IBM Power5, each of which has made

separate bets on exploiting ILP and TLP. While the last edition contained a great

deal on Itanium, we moved much of this material to Appendix G, indicating our

view that this architecture has not lived up to the early claims.

Given the switch in the ﬁeld from exploiting only ILP to an equal focus on

thread- and data-level parallelism, we moved multiprocessor systems up to Chap-

ter 4, which focuses on shared-memory architectures. The chapter begins with

the performance of such an architecture. It then explores symmetric and

distributed memory architectures, examining both organizational principles and

performance. Topics in synchronization and memory consistency models are

Preface ■ xix

next. The example is the Sun T1 (“Niagara”), a radical design for a commercial

product. It reverted to a single-instruction issue, 6-stage pipeline microarchitec-

ture. It put 8 of these on a single chip, and each supports 4 threads. Hence, soft-

ware sees 32 threads on this single, low-power chip.

As mentioned earlier, Appendix C contains an introductory review of cache

principles, which is available in case you need it. This shift allows Chapter 5 to

start with 11 advanced optimizations of caches. The chapter includes a new sec-

tion on virtual machines, which offers advantages in protection, software man-

agement, and hardware management. The example is the AMD Opteron, giving

both its cache hierarchy and the virtual memory scheme for its recently expanded

64-bit addresses.

Chapter 6, “Storage Systems,” has an expanded discussion of reliability and

availability, a tutorial on RAID with a description of RAID 6 schemes, and rarely

found failure statistics of real systems. It continues to provide an introduction to

queuing theory and I/O performance benchmarks. Rather than go through a series

of steps to build a hypothetical cluster as in the last edition, we evaluate the cost,

performance, and reliability of a real cluster: the Internet Archive. The “Putting It

All Together” example is the NetApp FAS6000 ﬁler, which is based on the AMD

Opteron microprocessor.

This brings us to Appendices A through L. As mentioned earlier, Appendices

A and C are tutorials on basic pipelining and caching concepts. Readers relatively

new to pipelining should read Appendix A before Chapters 2 and 3, and those

new to caching should read Appendix C before Chapter 5.

Appendix B covers principles of ISAs, including MIPS64, and Appendix J

describes 64-bit versions of Alpha, MIPS, PowerPC, and SPARC and their multi-

media extensions. It also includes some classic architectures (80x86, VAX, and

IBM 360/370) and popular embedded instruction sets (ARM, Thumb, SuperH,

MIPS16, and Mitsubishi M32R). Appendix G is related, in that it covers architec-

tures and compilers for VLIW ISAs.

Appendix D, updated by Thomas M. Conte, consolidates the embedded mate-

rial in one place.

Appendix E, on networks, has been extensively revised by Timothy M. Pink-

ston and José Duato. Appendix F, updated by Krste Asanovic, includes a descrip-

tion of vector processors. We think these two appendices are some of the best

material we know of on each topic.

Appendix H describes parallel processing applications and coherence proto-

cols for larger-scale, shared-memory multiprocessing. Appendix I, by David

Goldberg, describes computer arithmetic.

Appendix K collects the “Historical Perspective and References” from each

chapter of the third edition into a single appendix. It attempts to give proper

credit for the ideas in each chapter and a sense of the history surrounding the

inventions. We like to think of this as presenting the human drama of computer

design. It also supplies references that the student of architecture may want to

pursue. If you have time, we recommend reading some of the classic papers in

the ﬁeld that are mentioned in these sections. It is both enjoyable and educational

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