使用与门、全加器和半加器实现的32位乘法器设计

library ieee;
use ieee.std_logic_1164.all;
entity full_adder is 
  port(x,y,z:in std_logic;s,c:out std_logic);
end full_adder;
architecture df of full_adder is
begin
s<=(x xor y)xor z;
c<=(x and y)or(x and z)or(y and z);
end df;
--????????N???????
library ieee;
use ieee.std_logic_1164.all;
entity generic_fa is--------------------------------加法器
generic(n:natural);
    port(a,b:in std_logic_vector(n-1 downto 0);
        sum:out std_logic_vector(n-1 downto 0);
        cout:out std_logic);
end generic_fa;

architecture conc of generic_fa is
  component full_adder
    port(x,y,z:in std_logic;s,c:out std_logic);
  end component;
  signal carry:std_logic_vector(n downto 0);
begin
  carry(0)<='0';
  cout<=carry(n);
  
  g1:for k in 0 to n-1 generate

   fa:full_adder port map (x=>a(k),y=>b(k),z=>carry(k),
                        s=>sum(k),c=>carry(k+1));
                    end generate;
end conc;    
--????????????
library ieee;
use ieee.std_logic_1164.all;
entity mul24 is------------------------------------------------24位乘法（尾数相乘）
    port(mplr:in std_logic_vector(23 downto 0);
         mpcd:in std_logic_vector(23 downto 0);
 result_24:out std_logic_vector(23 downto 0));
end mul24;

architecture compact of mul24 is
  signal acarry:std_logic_vector(23 downto 0);
  type sum_type is array(23 downto 0) of
    std_logic_vector(23 downto 0);
  signal asum:sum_type;
  signal opd1,opd2:sum_type;
  signal res:std_logic_vector(47 downto 0);
  signal result:std_logic_vector(47 downto 0);
  
  function resize(a:in std_logic;size:in natural)--------------------------res="0000..0"或者"1111..1"
    return std_logic_vector is
    variable res:std_logic_vector(size-1 downto 0);
begin 
    res:=(others=>a);
    return(res);
end;