24LC32A: Microchip 低功耗2-Wire Serial EEPROM技术规格

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"24LC32A是一款由Microchip Technology Inc.生产的24系列32Kbit电可擦除只读存储器（EEPROM）。" 24LC32A是微芯科技推出的一款低功耗、两线制串行接口的EEPROM芯片，其主要特性包括： 1. **电源兼容性**：24AA32AF设备可在1.7V的单电源下工作，而24LC32AF则需要2.5V。这使得它们能够在各种电压环境下正常运行。 2. **低功耗CMOS技术**：在读取操作时，电流最大400μA；在待机状态下，电流最大1μA（在I-temp条件下），显著降低了能耗。 3. **两线制串行接口（I2C兼容）**：24LC32A支持I2C协议，能够与系统中的其他I2C设备共存并进行通信。 4. **级联功能**：采用3个地址引脚的封装，最多可以级联8个设备，扩展存储容量。 5. **施密特触发输入**：提供噪声抑制功能，确保信号的稳定传输。 6. **输出斜率控制**：通过控制输出斜率来消除地线反弹，提高系统的稳定性。 7. **时钟兼容性**：兼容100kHz和400kHz的时钟频率，适应不同速度的需求。 8. **快速写入**：页面写入时间最大5毫秒，提高了数据写入效率。 9. **自定时擦除/写入周期**：设备内部有自我定时的擦除和写入循环，无需外部时序控制。 10. **32字节页写缓冲区**：允许一次性写入多个字节，提高了批量写入的效率。 11. **硬件写保护**：对1/4数组（C00h-FFFh）提供硬件写保护，防止意外修改关键数据。 12. **静电放电保护**：ESD保护等级超过4,000V，增强设备在恶劣环境下的抗干扰能力。 13. **耐用性**：超过100万次的擦写周期，确保了长期使用的可靠性。 14. **数据保留时间**：数据保留时间超过200年，即使在断电情况下也能保持数据不丢失。 15. **封装形式**：24LC32A提供8引脚PDIP、SOIC、TSSOP、MSOP、TDFN和5引脚SOT-23等多种封装选择，满足不同设计需求。 16. **环保认证**：符合无铅和RoHS标准，确保产品符合环保要求。 17. **温度范围**：工业级（I）设备的工作温度范围为-40°C至+85°C，汽车级（E）设备的工作温度范围更宽，为-40°C至+125°C，适合严苛环境应用。这款EEPROM芯片广泛应用于需要非易失性存储的场合，如嵌入式系统、汽车电子、工业控制系统等，提供可靠的数据存储解决方案。

24AA32AF/24LC32AF

3.0 FUNCTIONAL DESCRIPTION

The 24XX32AF supports a bidirectional, 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, while a device

receiving data is defined as a receiver. The bus has to

be controlled by a master device which generates the

Serial Clock (SCL), controls the bus access and gener-

ates the Start and Stop conditions, while the 24XX32AF

works as slave. Both master and slave can operate as

transmitter or receiver, but the master device

determines which mode is activated.

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 4-1).

4.1 Bus Not Busy (A)

Both data and clock lines remain high.

4.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

4.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

4.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of data

bytes transferred between Start and Stop conditions is

determined by the master device and is, theoretically,

unlimited (although only the last thirty-two bytes will be

stored when doing a write operation). When an over-

write does occur, it will replace data in a first-in first-out

(FIFO) fashion.

4.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an Acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

The device that acknowledges, has to pull down the

SDA line during the Acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the Acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24XX32AF) will leave the data

line high to enable the master to generate the Stop

condition.

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24XX32AF does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

SCL

SDA

(A) (B) (D) (D) (A)(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

24AA32AF/24LC32AF

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the

Start condition from the master device (Figure 5-1).

The control byte consists of a four-bit control code. For

the 24XX32AF, this is set as ‘1010’ binary for read and

write operations. The next three bits of the control byte

are the Chip Select bits (A2, A1, A0). The Chip Select

bits allow the use of up to eight 24XX32AF devices on

the same bus and are used to select which device is

accessed. The Chip Select bits in the control byte must

correspond to the logic levels on the corresponding A2,

A1 and A0 pins for the device to respond. These bits

are in effect the three Most Significant bits of the word

address.

For the SOT-23 package, the address pins are not

available. During device addressing, the A1, A2, and

A0 Chip Select bits (Figure 5-2) should be set to ‘0’.

The last bit of the control byte defines the operation to

be performed. When set to a ‘1’, a read operation is

selected. When set to a zero, a write operation is

selected. The next two bytes received define the

address of the first data byte (Figure 5-2). Because

only A11 to A0 are used, the upper four address bits are

“don’t care” bits. The upper address bits are transferred

first, followed by the Less Significant bits.

Following the Start condition, the 24XX32AF monitors

the SDA bus checking the device type identifier being

transmitted and, upon receiving a ‘1010’ code and

appropriate device select bits, the slave device outputs

an Acknowledge signal on the SDA line. Depending on

the state of the R/W

bit, the 24XX32AF will select a

read or write operation.

FIGURE 5-1: CONTROL BYTE FORMAT

5.1 Contiguous Addressing Across

Multiple Devices

The Chip Select bits A2, A1 and A0 can be used to

expand the contiguous address space for up to 256K

bits by adding up to eight 24XX32AF devices on the

same bus. In this case, software can use A0 of the con-

trol byte as address bit A12; A1 as address bit A13; and

A2 as address bit A14. It is not possible to sequentially

read across device boundaries.

The SOT-23 package does not support multiple device

addressing on the same bus.

FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

1010A2 A1 A0SACK

R/W

Control Code

Chip Select

Bits

Slave Address

Acknowledge Bit

Start Bit

Read/Write Bit

1010

R/W xxxx

••••••

Control Byte Address High Byte Address Low Byte

Control

Code

Chip

Select

Bits

x = “don’t care” bit

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