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首页GD32F30x Cortex-M4微控制器用户手册v2.3:FMC功能详解
GD32F30x User Manual 是来自GigaDevice Semiconductor Inc.的一款基于ARM Cortex-M4的24位微控制器GD32F303的官方用户手册。该手册适用于GD32F30x系列,特别是F303型号,发布于2020年3月,版本号为2.3。手册详尽地介绍了该设备的系统架构、内存布局、以及Flash Memory Controller (FMC)的功能和操作。
1. **系统与内存架构**:
- 该文档首先概述了处理器架构,强调了GD32F30x采用ARM Cortex-M4,这是一种高性能、低功耗的32位微控制器,适合各种嵌入式应用。
- 系统架构部分详细解释了微控制器内部的硬件配置,包括存储器映射,其中提到了Bit-banding技术,一种将数据存储在特定位置以优化性能的技术。
- 内置内存包括on-chip SRAM(片内随机访问存储器)和on-chip flash memory(闪存),手册还讨论了不同内存区域的用途和特性。
- 启动配置被提及,可能涉及引导加载程序和固件初始化的过程。
- 设备电子签名部分提供了关于内存密度和96位唯一设备标识的信息,这对于设备识别和调试至关重要。
2. **Flash Memory Controller (FMC)**:
- FMC是GD32F30x的核心组件之一,负责管理闪存操作。
- FMC介绍部分概述了其主要功能和目的,包括提供高效的编程和擦除选项。
- 功能描述深入到具体操作细节:
- Flash memory architecture描述了闪存存储器的结构,可能涉及到页大小、块结构等。
- 读取操作指导用户如何从闪存中读取数据。
- 用户需要了解如何解锁特定的FMC CTLx寄存器来控制不同的功能。
- Page erase(单个页面擦除)和Mass erase(全芯片擦除)操作的步骤。
- 主闪存编程,可能包括批量编程和分段编程的说明。
- 选项字节(Option Bytes)涉及非易失性存储器的自定义配置,如配置寄存器、密码保护和安全设置。
- 提供了页擦除和编程保护,以及关于如何确保数据安全和防止未经授权的修改。
- 安全保护机制的描述,可能包括固件保护、加密和访问控制等。
通过阅读GD32F30x User Manual,开发人员可以全面了解如何配置和操作这个微控制器,包括它的硬件特性、内存管理以及对Flash Memory Controller的深入操作,这对于硬件设计、软件开发和调试工作来说都是极其重要的参考资料。
GD32F30x User Manual
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23.3. Function overview .................................................................................................... 695
23.3.1. Interface configuration ................................................................................................................... 695
23.3.2. MAC function overview .................................................................................................................. 699
23.3.3. MAC statistics counters: MSC ...................................................................................................... 711
23.3.4. Wake up management: WUM ....................................................................................................... 711
23.3.5. Precision time protocol: PTP ......................................................................................................... 715
23.3.6. DMA controller description ............................................................................................................ 719
23.3.7. Example for a typical configuration flow of Ethernet ................................................................. 744
23.3.8. Ethernet interrupts .......................................................................................................................... 746
23.4. Register definition .................................................................................................... 748
23.4.1. MAC configuration register (ENET_MAC_CFG) ........................................................................ 748
23.4.2. MAC frame filter register (ENET_MAC_FRMF) ......................................................................... 750
23.4.3. MAC hash list high register (ENET_MAC_HLH) ........................................................................ 752
23.4.4. MAC hash list low register (ENET_MAC_HLL) .......................................................................... 752
23.4.5. MAC PHY control register (ENET_MAC_PHY_CTL) ................................................................ 753
23.4.6. MAC MII data register (ENET_MAC_PHY_DATA) .................................................................... 754
23.4.7. MAC flow control register (ENET_MAC_FCTL) ......................................................................... 754
23.4.8. MAC VLAN tag register (ENET_MAC_VLT) ............................................................................... 756
23.4.9. MAC remote wakeup frame filter register (ENET_MAC_RWFF) ............................................. 756
23.4.10. MAC wakeup management register (ENET_MAC_WUM) ................................................... 757
23.4.11. MAC debug register (ENET_MAC_DBG) ............................................................................... 758
23.4.12. MAC interrupt flag register (ENET_MAC_INTF) .................................................................... 760
23.4.13. MAC interrupt mask register (ENET_MAC_INTMSK) ........................................................... 761
23.4.14. MAC address 0 high register (ENET_MAC_ADDR0H) ........................................................ 761
23.4.15. MAC address 0 low register (ENET_MAC_ADDR0L) ........................................................... 762
23.4.16. MAC address 1 high register (ENET_MAC_ADDR1H) ........................................................ 762
23.4.17. MAC address 1 low register (ENET_MAC_ADDR1L) ........................................................... 763
23.4.18. MAC address 2 high register (ENET_MAC_ADDR2H) ........................................................ 763
23.4.19. MAC address 2 low register (ENET_MAC_ADDR2L) ........................................................... 764
23.4.20. MAC address 3 high register (ENET_MAC_ADDR3H) ........................................................ 765
23.4.21. MAC address 3 low register (ENET_MAC_ADDR3L) ........................................................... 766
23.4.22. MAC flow control threshold register (ENET_MAC_FCTH) ................................................... 766
23.4.23. MSC control register (ENET_MSC_CTL) ............................................................................... 767
23.4.24. MSC receive interrupt flag register (ENET_MSC_RINTF) ................................................... 768
23.4.25. MSC transmit interrupt flag register (ENET_MSC_TINTF) .................................................. 768
23.4.26. MSC receive interrupt mask register (ENET_MSC_RINTMSK) .......................................... 769
23.4.27. MSC transmit interrupt mask register (ENET_MSC_TINTMSK) ......................................... 770
23.4.28. MSC transmitted good frames after a single collision counter register
(ENET_MSC_SCCNT) ................................................................................................................................... 771
23.4.29. MSC transmitted good frames after more than a single collision counter register
(ENET_MSC_MSCCNT) ................................................................................................................................ 771
23.4.30. MSC transmitted good frames counter register (ENET_MSC_TGFCNT).......................... 772
23.4.31. MSC received frames with CRC error counter register (ENET_MSC_RFCECNT) .......... 772
GD32F30x User Manual
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23.4.32. MSC received frames with alignment error counter register (ENET_MSC_RFAECNT) .. 772
23.4.33. MSC received good unicast frames counter register (ENET_MSC_RGUFCNT) ............. 773
23.4.34. PTP time stamp control register (ENET_PTP_TSCTL) ........................................................ 773
23.4.35. PTP subsecond increment register (ENET_PTP_SSINC) ................................................... 776
23.4.36. PTP time stamp high register (ENET_PTP_TSH) ................................................................. 776
23.4.37. PTP time stamp low register (ENET_PTP_TSL) ................................................................... 777
23.4.38. PTP time stamp update high register (ENET_PTP_TSUH) ................................................. 777
23.4.39. PTP time stamp update low register (ENET_PTP_TSUL) ................................................... 778
23.4.40. PTP time stamp addend register (ENET_PTP_TSADDEND) ............................................. 778
23.4.41. PTP expected time high register (ENET_PTP_ETH) ............................................................ 779
23.4.42. PTP expected time low register (ENET_PTP_ETL) .............................................................. 779
23.4.43. PTP time stamp flag register (ENET_PTP_TSF) ................................................................... 779
23.4.44. PTP PPS control register (ENET_PTP_PPSCTL) ................................................................. 780
23.4.45. DMA bus control register (ENET_DMA_BCTL) ..................................................................... 781
23.4.46. DMA transmit poll enable register (ENET_DMA_TPEN) ...................................................... 783
23.4.47. DMA receive poll enable register (ENET_DMA_RPEN) ....................................................... 783
23.4.48. DMA receive descriptor table address register (ENET_DMA_RDTADDR) ........................ 784
23.4.49. DMA transmit descriptor table address register (ENET_DMA_TDTADDR) ....................... 784
23.4.50. DMA status register (ENET_DMA_STAT) ............................................................................... 785
23.4.51. DMA control register (ENET_DMA_CTL) ................................................................................ 788
23.4.52. DMA interrupt enable register (ENET_DMA_INTEN) ........................................................... 791
23.4.53. DMA missed frame and buffer overflow counter register (ENET_DMA_MFBOCNT) ...... 793
23.4.54. DMA receive state watchdog counter register (ENET_DMA_RSWDC) ............................. 794
23.4.55. DMA current transmit descriptor address register (ENET_DMA_CTDADDR) .................. 794
23.4.56. DMA current receive descriptor address register (ENET_DMA_CRDADDR) ................... 795
23.4.57. DMA current transmit buffer address register (ENET_DMA_CTBADDR) .......................... 795
23.4.58. DMA current receive buffer address register (ENET_DMA_CRBADDR) ........................... 796
24. Universal Serial Bus full-speed device interface (USBD) ............................... 797
24.1. Overview .................................................................................................................... 797
24.2. Main features ............................................................................................................. 797
24.3. Block diagram ........................................................................................................... 797
24.4. Signal description .................................................................................................... 798
24.5. Clock configuration .................................................................................................. 798
24.6. Function overview .................................................................................................... 799
24.6.1. USB endpoints ................................................................................................................................ 799
24.6.2. Operation procedure ...................................................................................................................... 801
24.6.3. USB events and interrupts ............................................................................................................ 804
24.6.4. Operation guide............................................................................................................................... 806
24.7. Registers definition .................................................................................................. 808
24.7.1. USBD control register (USBD_CTL) ............................................................................................ 808
24.7.2. USBD interrupt flag register (USBD_INTF) ................................................................................ 810
GD32F30x User Manual
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24.7.3. USBD status register (USBD_STAT) ........................................................................................... 811
24.7.4. USBD device address register (USBD_DADDR)....................................................................... 811
24.7.5. USBD buffer address register (USBD_BADDR) ........................................................................ 812
24.7.6. USBD endpoint x control and status register (USBD_EPxCS), x=[0..7] ................................ 812
24.7.7. USBD endpoint x transmission buffer address register (USBD_EPxTBADDR), x can be in
[0..7] 814
24.7.8. USBD endpoint x transmission buffer byte count register (USBD_EPxTBCNT), x can be in
[0..7] 815
24.7.9. USBD endpoint x reception buffer address register (USBD_EPxRBADDR), x can be in
[0..7] 815
24.7.10. USBD endpoint x reception buffer byte count register (USBD_EPxRBCNT), x can be in
[0..7] 816
24.7.11. USBD LPM control and status register (USBD_LPMCS) ..................................................... 816
25. Universal serial bus full-speed interface (USBFS) .......................................... 818
25.1. Overview ...................................................................................................................... 818
25.2. Characteristics .............................................................................................................. 818
25.3. Block diagram ............................................................................................................... 819
25.4. Signal description ......................................................................................................... 819
25.5. Function overview ........................................................................................................ 819
25.5.1. USBFS clocks and working modes .............................................................................................. 819
25.5.2. USB host function ........................................................................................................................... 821
25.5.3. USB device function ....................................................................................................................... 823
25.5.4. OTG function overview .................................................................................................................. 824
25.5.5. Data FIFO ........................................................................................................................................ 825
25.5.6. Operation guide............................................................................................................................... 827
25.6. Interrupts ..................................................................................................................... 832
25.7. Register definition ........................................................................................................ 834
25.7.1. Global control and status registers ............................................................................................... 834
25.7.2. Host control and status registers .................................................................................................. 855
25.7.3. Device control and status registers .............................................................................................. 867
25.7.4. Power and clock control register (USBFS_PWRCLKCTL) ....................................................... 891
26. Revision history .................................................................................................... 893
GD32F30x User Manual
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List of Figures
Figure 1-1. The structure of the Cortex™-M4 processor .......................................................................... 32
Figure 1-2. GD32F303 series system architecture ..................................................................................... 34
Figure 1-3. GD32F305 and GD32F307 series system architecture .......................................................... 35
Figure 2-1. Process of page erase operation .............................................................................................. 47
Figure 2-2. Process of mass erase operation ............................................................................................. 48
Figure 2-3. Process of word program operation ........................................................................................ 50
Figure 3-1. Power supply overview ............................................................................................................... 64
Figure 3-2. Waveform of the POR/PDR ......................................................................................................... 66
Figure 3-3. Waveform of the LVD threshold ................................................................................................ 66
Figure 5-1. The system reset circuit ............................................................................................................. 81
Figure 5-2. Clock tree ...................................................................................................................................... 82
Figure 5-3. HXTAL clock source .................................................................................................................... 83
Figure 5-4. The system reset circuit ........................................................................................................... 115
Figure 5-5. Clock tree .................................................................................................................................... 116
Figure 5-6. HXTAL clock source .................................................................................................................. 118
Figure 6-1. CTC overview .............................................................................................................................. 155
Figure 6-2. CTC trim counter ........................................................................................................................ 156
Figure 7-1. Block diagram of EXTI .............................................................................................................. 169
Figure 8-1. Basic structure of a standard I/O port bit .............................................................................. 175
Figure 8-2. Input configuration .................................................................................................................... 177
Figure 8-3. Output configuration ................................................................................................................. 177
Figure 8-4. Analog configuration ................................................................................................................. 178
Figure 8-5. Alternate function configuration ............................................................................................. 179
Figure 9-1. Block diagram of CRC calculation unit .................................................................................. 210
Figure 10-1. Block diagram of DMA ............................................................................................................ 214
Figure 10-2. Handshake mechanism .......................................................................................................... 216
Figure 10-3. DMA interrupt logic ................................................................................................................. 218
Figure 10-4. DMA0 request mapping .......................................................................................................... 219
Figure 10-5. DMA1 request mapping .......................................................................................................... 220
Figure 12-1. ADC module block diagram ................................................................................................... 237
Figure 12-2. Single conversion mode ......................................................................................................... 238
Figure 12-3. Continuous conversion mode ............................................................................................... 239
Figure 12-4. Scan conversion mode, continuous disable ...................................................................... 241
Figure 12-5. Scan conversion mode, continuous enable ....................................................................... 241
Figure 12-6. Discontinuous conversion mode .......................................................................................... 242
Figure 12-7. Auto-insertion, CNT = 1 .......................................................................................................... 243
Figure 12-8. Triggered insertion .................................................................................................................. 243
Figure 12-9. 12-bit Data alignment .............................................................................................................. 244
Figure 12-10. 6-bit Data alignment .............................................................................................................. 245
Figure 12-11. 20-bit to 16-bit result truncation .......................................................................................... 248
GD32F30x User Manual
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Figure 12-12. Numerical example with 5-bits shift and rounding .......................................................... 249
Figure 12-13. ADC sync block diagram ...................................................................................................... 250
Figure 12-14. Regular parallel mode on 16 channels............................................................................... 251
Figure 12-15. Inserted parallel mode on 4 channels ................................................................................ 252
Figure 12-16. Follow-up fast mode on 1 channel in continuous conversion mode ........................... 252
Figure 12-17. Follow-up slow mode on 1 channel .................................................................................... 253
Figure 12-18. Trigger rotation: inserted channel group .......................................................................... 254
Figure 12-19. Trigger rotation: inserted channels in discontinuous mode ......................................... 254
Figure 12-20. Regular parallel & trigger rotation mode ........................................................................... 255
Figure 12-21. Trigger occurs during inserted conversion ...................................................................... 255
Figure 12-22 Follow-up single channel with inserted sequence CH1, CH2 ......................................... 255
Figure 13-1. DAC block diagram .................................................................................................................. 272
Figure 13-2. DAC LFSR algorithm ............................................................................................................... 274
Figure 13-3. DAC triangle noise wave ........................................................................................................ 274
Figure 14-1. Free watchdog block diagram ............................................................................................... 286
Figure 14-2. Window watchdog timer block diagram .............................................................................. 292
Figure 14-3. Window watchdog timing diagram ....................................................................................... 293
Figure 15-1. Block diagram of RTC ............................................................................................................. 297
Figure 16-1. Advanced timer block diagram ............................................................................................. 307
Figure 16-2. Normal mode, internal clock divided by 1 ........................................................................... 308
Figure 16-3. Counter timing diagram with prescaler division change from 1 to 2 ............................. 309
Figure 16-4. Up-counter timechart, PSC=0/1 ............................................................................................. 310
Figure 16-5. Up-counter timechart, change TIMERx_CAR on the go .................................................... 311
Figure 16-6. Down-counter timechart, PSC=0/1 ........................................................................................ 312
Figure 16-7. Down-counter timechart, change TIMERx_CAR on the go .............................................. 313
Figure 16-8. Center-aligned counter timechart ......................................................................................... 314
Figure 16-9. Repetition timechart for center-aligned counter ................................................................ 315
Figure 16-10. Repetition timechart for up-counter ................................................................................... 315
Figure 16-11. Repetition timechart for down-counter .............................................................................. 316
Figure 16-12. Input capture logic ................................................................................................................. 317
Figure 16-13. Output-compare under three modes .................................................................................. 319
Figure 16-14. EAPWM timechart .................................................................................................................. 320
Figure 16-15. CAPWM timechart .................................................................................................................. 320
Figure 16-16. Complementary output with dead-time insertion. ........................................................... 323
Figure 16-17. Output behavior in response to a break(The break high active) ................................... 324
Figure 16-18. Example of counter operation in encoder interface mode ............................................. 325
Figure 16-19. Example of encoder interface mode with CI0FE0 polarity inverted ............................. 325
Figure 16-20. Hall sensor is used to BLDC motor .................................................................................... 327
Figure 16-21. Hall sensor timing between two timers ............................................................................. 327
Figure 16-22. Restart mode .......................................................................................................................... 328
Figure 16-23. Pause mode ............................................................................................................................ 329
Figure 16-24. Event mode ............................................................................................................................. 329
Figure 16-25. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 .................................. 330
Figure 16-26. Timer0 master/slave mode timer example ........................................................................ 331
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