DDR3 SDRAM规格详解：MT41J系列

5星 · 超过95%的资源需积分: 50 12 浏览量更新于2024-07-14 收藏 2.89MB PDF 举报

"MT41J256M16HA-125_E.pdf" 是一份关于DDR3 SDRAM的规格说明书，其中详细描述了内存芯片的不同型号和特性，适用于低功耗应用。 DDR3 SDRAM（Double Data Rate Third Generation Synchronous Dynamic Random-Access Memory）是一种高速、同步的动态随机存取存储器，广泛用于计算机和其他电子设备中。DDR3的主要特点是其双倍数据速率，即在时钟周期的上升沿和下降沿都能传输数据，从而提高了数据传输速率。 1. **电压与I/O接口**：DDR3 SDRAM工作在1.5V±0.075V的电压下，VDD和VDDQ都保持在这个范围内。I/O接口采用中心终止的推挽式（push/pull）设计，并使用差分信号，这有助于减少信号干扰，提高信号质量。 2. **数据传输**：数据通过双向差分数据 strobe进行传输，8n位预取架构允许在每个时钟周期内处理更多数据，提高了性能。同时，它有8个内部银行，可以并行处理多个数据请求。 3. **时序特性**：该内存支持可编程的读取CAS延迟（CL）、附加CAS延迟（AL）和基于时钟周期的写入CAS延迟（CWL）。固定突发长度（BL）为8，突发切片（BC）为4，可通过模式寄存器集（MRS）进行配置。此外，还支持在运行时选择BC4或BL8。 4. **自刷新功能**：在自刷新模式下，内存可以在无需CPU控制的情况下保持数据完整性。根据温度范围，自刷新周期会有所不同，例如，在0°C至85°C时，需要每64ms进行8192次刷新循环，而在85°C至95°C时，这一频率增加到每32ms。 5. **其他特性**：还包括自刷新温度（SRT）选项，以适应不同的工作环境。写入校准和输出驱动器校准确保了数据的准确传输。此外，还有多功能寄存器以支持各种配置选项。 6. **封装和选项**：MT41J系列有不同容量的版本，如1Gigabit x4（MT41J1G4），512Megabit x8（MT41J512M8）和256Megabit x16（MT41J256M16）。它们被封装在无铅的FBGA（Fine Pitch Ball Grid Array）封装中，有不同尺寸和引脚数的选择，如78-ball和96-ball封装。这份文档提供了关于DDR3 SDRAM的详细技术规格，对设计和使用这类内存的工程师来说是重要的参考资料。了解这些特性有助于优化系统性能，确保兼容性和稳定性。

Figure 5: 256 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[14:0]

BA[2:0]

Address

(128

x128)

16,384

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(32,768 x 128 x 128)

Bank 0

row-

address

latch

and

decoder

32,768

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

128

LDQS, LDQS#, UDQS, UDQS#

Column 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

BC4

READ

drivers

DQ[15:0]

READ

FIFO

and

data

MUX

Data

BC4 (burst chop)

Bank 1

Bank 2

Bank 3

LDM/UDM

CK, CK#

LDQS, LDQS#

UDQS, UDQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[15:0]

(1 . . . 16)

(1 . . . 4)

(1, 2)

sw1

sw2

DDQ

TT,nom

TT(WR)

BC4

sw1

sw2

DDQ

TT,nom

TT(WR)

sw1

sw2

DDQ

TT,nom

TT(WR)

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

ODT

control

SSQ

A12

OTF

4Gb: x4, x8, x16 DDR3 SDRAM

Functional Block Diagrams

PDF: 09005aef8417277b

4Gb_DDR3_SDRAM.pdf - Rev. M 4/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 3).

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A[15:13], A12/BC#,

A11, A10/AP, A[9:0]

Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank

(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also

provide the op-code during a LOAD MODE command. Address inputs are referenced

to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 69 (page 115).

BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode

BA[2:0] are referenced to V

REFCA

CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of

CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW)

internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/

disabled is dependent upon the DDR3 SDRAM configuration and operating mode.

Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations

(all banks idle), or active power-down (row active in any bank). CKE is synchronous

for power-down entry and exit and for self refresh entry. CKE is asynchronous for

self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are

disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disa-

bled during SELF REFRESH. CKE is referenced to V

REFCA

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to V

REFCA

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with the input data during a write access.

Although the DM ball is input-only, the DM loading is designed to match that of the

DQ and DQS balls. DM is referenced to V

REFDQ

. DM has an optional use as TDQS on

the x8.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,

and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is

ignored if disabled via the LOAD MODE command. ODT is referenced to V

REFCA

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

4Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef8417277b

4Gb_DDR3_SDRAM.pdf - Rev. M 4/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)

Symbol Type Description

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V

and

DC LOW ≤ 0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are

referenced to V

REFDQ

DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are

referenced to V

REFDQ

DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write

data. Center-aligned to write data.

TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is

enabled, DM is disabled, and the TDQS and TDQS# balls provide termination

resistance.

Supply Power supply: 1.5V ±0.075V.

DDQ

Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immuni-

ty.

REFCA

Supply Reference voltage for control, command, and address: V

REFCA

must be

maintained at all times (including self refresh) for proper device operation.

REFDQ

Supply Reference voltage for data: V

REFDQ

must be maintained at all times (excluding self

refresh) for proper device operation.

Supply Ground.

SSQ

Supply DQ ground: Isolated on the device for improved noise immunity.

ZQ Reference External reference ball for output drive calibration: This ball is tied to an

external 240Ω resistor (RZQ), which is tied to V

SSQ

NC – No connect: These balls should be left unconnected (the ball has no connection to

the DRAM or to other balls).

NF – No function: When configured as a x4 device, these balls are NF. When configured

as a x8 device, these balls are defined as TDQS#, DQ[7:4].

4Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef8417277b

4Gb_DDR3_SDRAM.pdf - Rev. M 4/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

剩余212页未读，继续阅读

老孟9527

粉丝: 1
资源: 13

DDR3 SDRAM规格详解：MT41J系列

镁光 MT41J256M16型号DDR3数据手册

镁光DDR3 MT41J128M16数据手册

mt41j256m16ha-125:e

MT41J256M16HA-125

mt41j256m16ha-125数据手册

libboost_atomic-vc142-mt-gd-x64-1_78.lib libboost_atomic-vc142-mt-x64-1_78.lib 啥区别

MT41J256m16XX-125

MT41K256M16HA_125IT

matlab boost_thread-vc120-mt-1_56.dll下载

MT41K256M16XX-107

最新资源