Functional Description
7
May 2006 SLES043A
3 Functional Description
3.1 Input Multiplexers and Buffers
The TVP5150 device has an analog input channel that accepts two video inputs, ac-coupled through 0.1-µF
to 1-µF capacitors. The two analog input ports can be connected as follows:
• Two selectable composite video inputs or
• One S-video input
The internal video multiplexers can be configured via I
2
C. The internal nodes are grounded for zero channel
crosstalk. The input buffers are continuous time amplifiers that allow an input range of up to 0.75 V
PP
. This
allows the decoder to support input ranges of 0 to 1.5 V with an external attenuation of one-half.
3.2 Clamp
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The clamping circuit
provides line-by-line restoration of the video sync level to a fixed dc reference voltage. Two modes of clamping
are provided, coarse and fine.
• In coarse mode, the most negative portion of the input signal (typically the sync tip) is clamped to a fixed
dc level and remains on. This mode is used while the timing processor is searching for the horizontal sync.
• Fine clamp mode is enabled after the horizontal lock is achieved. This is enabled to prevent spurious level
shifting caused by noise more negative than the sync tip on the input signal. If fine clamp mode is selected,
then clamping is only enabled during the sync period.
− When in bottom level mode, the sync tip of the input signal is set to output code 0 of the A/D converter
(ADC).
− When in mid-level mode, fine clamp restores the dc level of the signal to the mid-range of the ADC.
S-video requires the fine clamp mode on the chroma channel for proper operation. The clamp can be
completely disabled using software registers.
3.3 Programmable Gain Amplifier and Automatic Gain Control Circuit
The programmable gain amplifier (PGA) and the automatic gain control (AGC) circuit work together to make
sure that the input signal is amplified sufficiently to ensure the proper input range for the ADC. The gain is
controlled by a 4-bit gain code.
Input video signal amplitude can vary significantly from the nominal level of 1 V
PP
(140 IRE). An AGC circuit
adjusts the signal amplitude to utilize the maximum range of the A/D converter without clipping. The AGC
adjusts the gain to achieve the desired sync amplitude. The PGA has a range of 0 to 12 dB.
3.4 A/D Converter
The ADC has 9 bits of resolution and runs at a maximum speed of 27 MHz. The clock input for the ADC comes
from the PLL. The data is aligned to the pixel clock supplied from the PLL and matched in delay. The ADC uses
the REFM and REFP terminals as the internal reference generator. For configuration of these terminals,
please refer to Figure 5−1.
3.5 Composite Processing Block Diagram
The composite processing block process NTSC/PAL signals into the YCbCr color space. Figure 3−1 explains
the basic architecture of this processing block.
Figure 3−1 illustrates the luminance/chrominance (Y/C) separation process in the TVP5150 device. The
composite video is multiplied by subcarrier signals in the quadrature modulator to generate color difference
signals U and V. U and V are then low-pass filtered to achieve the desired bandwidth and to reduce crosstalk,
by the color low-pass filters.
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