"TMS416809高速DRAM芯片规格及性能综述"

TI-TMS416809.pdf is a document detailing the specifications of the TMS416809 and TMS4178092097152-WORD BY 8-BIT HIGH-SPEED DRAMs. The document was first published in December 1995 and revised in March 1996 by Texas Instruments. The organization of the DRAM is 2097152 × 8, and it operates on a single 5V power supply with a ±10% tolerance. The performance ranges of the DRAM are as follows: - Access time for the TMS416809-60: 60ns, tRAC = 15ns, tCAC = 30ns, tAA = 25ns, tHPC = 30ns - Access time for the TMS416809-70: 70ns, tRAC = 18ns, tCAC = 35ns, tAA = 30ns, tHPC = 35ns - Access time for the TMS416809-80: 80ns, tRAC = 20ns, tCAC = 40ns, tAA = 35ns, tHPC = 35ns The DRAM also supports Extended Data Out (EDO) operation, CAS-Before-RAS (CBR) refresh, and a high-impedance state Unlatc. Overall, the TI-TMS416809.pdf provides detailed information on the specifications and performance of the TMS416809 and TMS4178092097152-WORD BY 8-BIT HIGH-SPEED DRAMs, making it a valuable resource for engineers and designers working with high-speed memory solutions.