Stellaris LM3S9B96 Microcontroller英文数据手册概览

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"LM3S9B96 英文版数据手册，包含了关于Texas Instruments生产的Stellaris LM3S9B96 微控制器的详细技术规格和功能描述。" 该手册首先介绍了文档修订历史、目标受众、手册概述、相关文档以及文档约定等基本信息。接着，它详细阐述了LM3S9B96微控制器的架构概述，包括以下关键知识点： 1. **架构概述**： LM3S9B96是一款基于ARM Cortex-M3处理器核心的微控制器，适用于各种嵌入式应用。 2. **目标应用**：它适用于需要高性能处理、高级运动控制、模拟功能以及串行通信的系统。 3. **特性**： - **ARM Cortex-M3处理器核心**：提供高效能、低功耗的处理能力。 - **片上内存**：包括闪存和SRAM，用于存储程序和工作数据。 - **外部外围接口**：支持与外部设备的连接，如GPIO、SPI、I2C等。 - **串行通信外设**：包含UART、I2C、SPI等多种接口，便于进行串行通信。 - **系统集成**：内置时钟系统、电源管理模块等，简化系统设计。 - **高级运动控制**：支持电机控制和其他精确定时任务。 - **模拟部分**：包括ADC、比较器等，实现模拟信号的处理。 - **JTAG和ARM串行线调试**：提供方便的硬件调试功能。 - **封装和温度范围**：提供了多种封装选项，适应不同环境的温度要求。 4. **硬件细节**：进一步详细描述了处理器的硬件结构，如块图、编程模型、处理器模式、特权级别、堆栈、寄存器映射等。手册的第二部分深入讨论了Cortex-M3处理器，包括其结构图、概述和编程模型。这部分详细介绍了处理器如何与系统接口、内置的调试配置、Trace Port Interface Unit (TPIU)以及Cortex-M3系统组件的详细信息。编程模型部分涵盖了软件执行的处理器模式和特权级别、堆栈的使用以及寄存器布局。这个数据手册对于开发者来说是至关重要的参考资料，它提供了设计和开发基于LM3S9B96微控制器的系统所需的全部技术信息。手册中还包括了生产数据信息，强调了TI标准保修条款，以及产品在关键应用中的使用注意事项。此外，手册还提供了技术支持链接，便于用户获取最新的产品信息和技术帮助。

Table 7-7. Channel Control Structure Offsets for Channel 30 ................................................ 361

Table 7-8. Channel Control Word Configuration for Memory Transfer Example ...................... 361

Table 7-9. Channel Control Structure Offsets for Channel 7 .................................................. 362

Table 7-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 363

Table 7-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 364

Table 7-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 365

Table 7-13. μDMA Register Map .......................................................................................... 366

Table 8-1. GPIO Pins With Non-Zero Reset Values .............................................................. 404

Table 8-2. GPIO Pins and Alternate Functions (100LQFP) ................................................... 404

Table 8-3. GPIO Pins and Alternate Functions (108BGA) ..................................................... 406

Table 8-4. GPIO Pad Configuration Examples ..................................................................... 412

Table 8-5. GPIO Interrupt Configuration Example ................................................................ 413

Table 8-6. GPIO Pins With Non-Zero Reset Values .............................................................. 414

Table 8-7. GPIO Register Map ........................................................................................... 414

Table 8-8. GPIO Pins With Non-Zero Reset Values .............................................................. 427

Table 8-9. GPIO Pins With Non-Zero Reset Values .............................................................. 433

Table 8-10. GPIO Pins With Non-Zero Reset Values .............................................................. 435

Table 8-11. GPIO Pins With Non-Zero Reset Values .............................................................. 438

Table 8-12. GPIO Pins With Non-Zero Reset Values .............................................................. 445

Table 9-1. External Peripheral Interface Signals (100LQFP) ................................................. 461

Table 9-2. External Peripheral Interface Signals (108BGA) ................................................... 462

Table 9-3. EPI SDRAM Signal Connections ......................................................................... 467

Table 9-4. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 471

Table 9-5. EPI Host-Bus 8 Signal Connections .................................................................... 472

Table 9-6. EPI Host-Bus 16 Signal Connections .................................................................. 474

Table 9-7. EPI General Purpose Signal Connections ........................................................... 483

Table 9-8. External Peripheral Interface (EPI) Register Map ................................................. 489

Table 10-1. Available CCP Pins ............................................................................................ 533

Table 10-2. General-Purpose Timers Signals (100LQFP) ....................................................... 534

Table 10-3. General-Purpose Timers Signals (108BGA) ......................................................... 535

Table 10-4. General-Purpose Timer Capabilities .................................................................... 536

Table 10-5. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 537

Table 10-6. 16-Bit Timer With Prescaler Configurations ......................................................... 538

Table 10-7. Counter Values When the Timer is Enabled in RTC Mode .................................... 539

Table 10-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 540

Table 10-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 541

Table 10-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 542

Table 10-11. Timers Register Map .......................................................................................... 547

Table 11-1. Watchdog Timers Register Map .......................................................................... 582

Table 12-1. ADC Signals (100LQFP) .................................................................................... 606

Table 12-2. ADC Signals (108BGA) ...................................................................................... 607

Table 12-3. Samples and FIFO Depth of Sequencers ............................................................ 608

Table 12-4. Differential Sampling Pairs ................................................................................. 615

Table 12-5. ADC Register Map ............................................................................................. 624

Table 13-1. UART Signals (100LQFP) .................................................................................. 686

Table 13-2. UART Signals (108BGA) .................................................................................... 686

Table 13-3. Flow Control Mode ............................................................................................. 692

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Table 13-4. UART Register Map ........................................................................................... 697

Table 14-1. SSI Signals (100LQFP) ...................................................................................... 750

Table 14-2. SSI Signals (108BGA) ........................................................................................ 750

Table 14-3. SSI Register Map .............................................................................................. 761

Table 15-1. I2C Signals (100LQFP) ...................................................................................... 791

Table 15-2. I2C Signals (108BGA) ........................................................................................ 791

Table 15-3. Examples of I

C Master Timer Period versus Speed Mode ................................... 795

Table 15-4. Inter-Integrated Circuit (I

C) Interface Register Map ............................................. 805

Table 15-5. Write Field Decoding for I2CMCS[3:0] Field ......................................................... 811

Table 16-1. I2S Signals (100LQFP) ...................................................................................... 830

Table 16-2. I2S Signals (108BGA) ........................................................................................ 830

Table 16-3. I

S Transmit FIFO Interface ................................................................................ 833

Table 16-4. Crystal Frequency (Values from 3.5795 MHz to 5 MHz) ........................................ 834

Table 16-5. Crystal Frequency (Values from 5.12 MHz to 8.192 MHz) ..................................... 834

Table 16-6. Crystal Frequency (Values from 10 MHz to 14.3181 MHz) .................................... 835

Table 16-7. Crystal Frequency (Values from 16 MHz to 16.384 MHz) ...................................... 835

Table 16-8. I

S Receive FIFO Interface ................................................................................. 837

Table 16-9. Audio Formats Configuration .............................................................................. 839

Table 16-10. Inter-Integrated Circuit Sound (I

S) Interface Register Map ................................... 840

Table 17-1. Controller Area Network Signals (100LQFP) ........................................................ 867

Table 17-2. Controller Area Network Signals (108BGA) ......................................................... 867

Table 17-3. Message Object Configurations .......................................................................... 873

Table 17-4. CAN Protocol Ranges ........................................................................................ 880

Table 17-5. CANBIT Register Values .................................................................................... 880

Table 17-6. CAN Register Map ............................................................................................. 884

Table 18-1. Ethernet Signals (100LQFP) ............................................................................... 918

Table 18-2. Ethernet Signals (108BGA) ................................................................................ 918

Table 18-3. TX & RX FIFO Organization ............................................................................... 921

Table 18-4. Ethernet Register Map ....................................................................................... 928

Table 19-1. USB Signals (100LQFP) .................................................................................... 978

Table 19-2. USB Signals (108BGA) ...................................................................................... 979

Table 19-3. Remainder (MAXLOAD/4) .................................................................................. 991

Table 19-4. Actual Bytes Read ............................................................................................. 991

Table 19-5. Packet Sizes That Clear RXRDY ........................................................................ 991

Table 19-6. Universal Serial Bus (USB) Controller Register Map ............................................ 993

Table 20-1. Analog Comparators Signals (100LQFP) ........................................................... 1117

Table 20-2. Analog Comparators Signals (108BGA) ............................................................. 1118

Table 20-3. Internal Reference Voltage and ACREFCTL Field Values ................................... 1120

Table 20-4. Analog Comparators Register Map ................................................................... 1121

Table 21-1. PWM Signals (100LQFP) ................................................................................. 1133

Table 21-2. PWM Signals (108BGA) ................................................................................... 1134

Table 21-3. PWM Register Map .......................................................................................... 1141

Table 22-1. QEI Signals (100LQFP) .................................................................................... 1208

Table 22-2. QEI Signals (108BGA) ..................................................................................... 1209

Table 22-3. QEI Register Map ............................................................................................ 1212

Table 24-1. GPIO Pins With Default Alternate Functions ...................................................... 1232

Table 24-2. Signals by Pin Number ..................................................................................... 1233

Table 24-3. Signals by Signal Name ................................................................................... 1245

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Stellaris

LM3S9B96 Microcontroller

Table 24-4. Signals by Function, Except for GPIO ............................................................... 1255

Table 24-5. GPIO Pins and Alternate Functions ................................................................... 1264

Table 24-6. Possible Pin Assignments for Alternate Functions .............................................. 1267

Table 24-7. Signals by Pin Number ..................................................................................... 1270

Table 24-8. Signals by Signal Name ................................................................................... 1282

Table 24-9. Signals by Function, Except for GPIO ............................................................... 1293

Table 24-10. GPIO Pins and Alternate Functions ................................................................... 1302

Table 24-11. Possible Pin Assignments for Alternate Functions .............................................. 1305

Table 24-12. Connections for Unused Signals (100-Pin LQFP) ............................................... 1308

Table 24-13. Connections for Unused Signals (108-Ball BGA) ................................................ 1309

Table 25-1. Temperature Characteristics ............................................................................. 1310

Table 25-2. Thermal Characteristics ................................................................................... 1310

Table 25-3. ESD Absolute Maximum Ratings ...................................................................... 1310

Table 26-1. Maximum Ratings ............................................................................................ 1311

Table 26-2. Recommended DC Operating Conditions .......................................................... 1311

Table 26-3. JTAG Characteristics ....................................................................................... 1312

Table 26-4. Power Characteristics ...................................................................................... 1314

Table 26-5. Reset Characteristics ....................................................................................... 1315

Table 26-6. LDO Regulator Characteristics ......................................................................... 1316

Table 26-7. Phase Locked Loop (PLL) Characteristics ......................................................... 1316

Table 26-8. Actual PLL Frequency ...................................................................................... 1317

Table 26-9. PIOSC Clock Characteristics ............................................................................ 1317

Table 26-10. 30-kHz Clock Characteristics ............................................................................ 1317

Table 26-11. Main Oscillator Clock Characteristics ................................................................ 1318

Table 26-12. Supported MOSC Crystal Frequencies .............................................................. 1318

Table 26-13. System Clock Characteristics with ADC Operation ............................................. 1319

Table 26-14. System Clock Characteristics with USB Operation ............................................. 1319

Table 26-15. Sleep Modes AC Characteristics ....................................................................... 1319

Table 26-16. Flash Memory Characteristics ........................................................................... 1319

Table 26-17. GPIO Module Characteristics ............................................................................ 1320

Table 26-18. EPI SDRAM Characteristics ............................................................................. 1320

Table 26-19. EPI SDRAM Interface Characteristics ............................................................... 1320

Table 26-20. EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics ................................. 1322

Table 26-21. EPI General-Purpose Interface Characteristics .................................................. 1324

Table 26-22. ADC Characteristics ......................................................................................... 1326

Table 26-23. ADC Module External Reference Characteristics ............................................... 1327

Table 26-24. ADC Module Internal Reference Characteristics ................................................ 1327

Table 26-25. SSI Characteristics .......................................................................................... 1327

Table 26-26. I

C Characteristics ........................................................................................... 1329

Table 26-27. I

S Master Clock (Receive and Transmit) .......................................................... 1330

Table 26-28. I

S Slave Clock (Receive and Transmit) ............................................................ 1330

Table 26-29. I

S Master Mode .............................................................................................. 1330

Table 26-30. I

S Slave Mode ................................................................................................ 1331

Table 26-31. Ethernet Controller DC Characteristics .............................................................. 1331

Table 26-32. 100BASE-TX Transmitter Characteristics .......................................................... 1332

Table 26-33. 100BASE-TX Transmitter Characteristics (informative) ....................................... 1332

Table 26-34. 100BASE-TX Receiver Characteristics .............................................................. 1332

Table 26-35. 10BASE-T Transmitter Characteristics .............................................................. 1332

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Table of Contents

List of Registers

The Cortex-M3 Processor ............................................................................................................. 78

Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 85

Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 85

Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 85

Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 85

Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 85

Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 85

Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 85

Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 85

Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 85

Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 85

Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 85

Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 85

Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 85

Register 14: Stack Pointer (SP) ........................................................................................................... 86

Register 15: Link Register (LR) ............................................................................................................ 87

Register 16: Program Counter (PC) ..................................................................................................... 88

Register 17: Program Status Register (PSR) ........................................................................................ 89

Register 18: Priority Mask Register (PRIMASK) .................................................................................... 93

Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 94

Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 95

Register 21: Control Register (CONTROL) ........................................................................................... 96

Cortex-M3 Peripherals ................................................................................................................. 121

Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 136

Register 5: Interrupt 32-54 Set Enable (EN1), offset 0x104 ................................................................ 137

Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 138

Register 7: Interrupt 32-54 Clear Enable (DIS1), offset 0x184 ............................................................ 139

Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 140

Register 9: Interrupt 32-54 Set Pending (PEND1), offset 0x204 ......................................................... 141

Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 142

Register 11: Interrupt 32-54 Clear Pending (UNPEND1), offset 0x284 .................................................. 143

Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 144

Register 13: Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304 ........................................................... 145

Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 146

Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 146

Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 146

Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 146

Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 146

Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 146

Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 146

Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 146

Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 146

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