SAA7150H与SAA7104H/SAA7105H数字视频编码器技术规格

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"SAA7150H的相关技术文档，主要涵盖了与其相关的SAA7104H和SAA7105H数字视频编码器的详细规格和技术特性。" SAA7150H虽然在提供的信息中没有直接提及，但我们可以推测这可能是一个与SAA7104H和SAA7105H类似的数字视频处理芯片。从描述中给出的SAA7104H和SAA7105H的datasheet内容来看，这两个芯片是数字视频编码器，广泛应用于视频处理和显示系统中。以下将详细解释这些芯片的关键功能和特性： 1. **特点**：这些芯片可能具有高精度的视频编码能力，支持多种输入格式和级别的转换，以及内置的Scaler和滤波器以提高图像质量。 2. **一般描述**：SAA7104H和SAA7105H是专为数字视频处理设计的集成电路，能够将各种视频信号转换为标准或高清晰度的电视输出格式。 3. **快速参考数据**：这部分提供关键的技术指标，如工作电压、功耗、输入/输出频率范围等。 4. **订购信息**：包含了芯片的封装类型、订单代码和其他购买相关的细节。 5. **模块图**：展示了芯片内部各个功能模块的布局和连接方式。 6. **引脚配置**：列出了每个引脚的功能，这对于正确连接和使用芯片至关重要。 7. **功能描述**：详细阐述了芯片的各个部分，如： - **重置条件**：定义了如何初始化或复位芯片。 - **输入格式化器**：处理不同格式的视频输入。 - **RGB查找表（LUT）**：用于色彩空间转换。 - **光标插入**：允许在视频流中添加图形或文本元素。 - **RGB到Y-CB-CR矩阵**：进行色彩空间转换，例如从RGB转为YUV。 - **水平和垂直Scaler**：调整视频的分辨率。 - **抗闪烁滤波器**：减少画面闪烁现象。 - **FIFO**：缓冲输入数据，确保稳定的输出。 - **边框生成器**：添加视频边框或黑边。 - **振荡器和离散时间振荡器（DTO）**：控制视频时钟和同步信号。 - **低通时钟生成电路（CGC）**：产生稳定低噪的时钟信号。 - **编码器**：将数字视频信号转换为模拟电视信号。 - **RGB处理器**：处理RGB视频信号。 - **三重DAC**：用于模拟输出的数模转换。 - **高清数据路径**：支持高清视频处理。 - **定时发生器**：生成视频同步信号。 - **模式发生器**：产生高清同步脉冲模式。 - **I2C总线接口**：实现与其他设备的通信和配置。 - **电源管理模式**：允许节能操作。 - **输入电平和格式**：支持不同的输入信号电平和格式。 - **位分配映射**：定义数据传输中的位分配。 - **I2C总线格式**：详细说明I2C通信协议。 - **从机接收器和发送器**：I2C总线上的角色定义。 8. **边界扫描测试**：一种用于检测芯片引脚电气特性的测试方法。 9. **限制值**：列出芯片在正常工作条件下可以承受的最大和最小参数值。由于原始信息中未提供SAA7150H的具体资料，以上内容主要基于SAA7104H和SAA7105H的特性进行推测。SAA7150H很可能具有类似的视频处理功能，但具体细节需参照其独立的数据手册。

2004 Mar 04 12

Philips Semiconductors Product speciﬁcation

Digital video encoder SAA7104H; SAA7105H

7.7 Vertical scaler and anti-ﬂicker ﬁlter

The functions scaling, Anti-Flicker Filter (AFF) and

re-interlacing are implemented in the vertical scaler.

Besides the entire input frame, it receives the first and last

lines of the border to allow anti-flicker filtering.

The circuit generates the interlaced output fields by scaling

down the input frames with different offsets for odd and

even fields. Increasing the YSKIP setting reduces the

anti-flicker function. A YSKIP value of 4095 switches it off;

see Table 85.

An additional, programmable vertical filter supports the

anti-flicker function. This filter is not available at upscaling

factors of more than 2.

The programming is similar to the horizontal scaler. For the

re-interlacing, the resolutions of the offset registers are not

sufficient, so the weighting factors for the first lines can

also be adjusted. YINC = 0 sets the scaling factor to 1;

YIWGTO and YIWGTE must not be 0.

Due to the re-interlacing, the circuit can perform upscaling

by a maximum factor of 2. The maximum factor depends

on the setting of the anti-flicker function and can be derived

from the formulae given in Section 7.20.

An additional upscaling mode allows to increase the

upscaling factor to maximum 4 as it is required for the old

VGA modes like 320 × 240.

7.8 FIFO

The FIFO acts as a buffer to translate from the PIXCLK

clock domain to the XTAL clock domain. The write clock is

PIXCLK and the read clock is XTAL. An underflow or

overflow condition can be detected via the I

C-bus read

access.

In order to avoid underflows and overflows, it is essential

that the frequency of the synthesized PIXCLK matches to

the input graphics resolution and the desired scaling

factor.

7.9 Border generator

When the graphics picture is to be displayed as interlaced

PAL, NTSC, S-video or RGB on a TV screen, it is desired

in many cases not to lose picture information due to the

inherent overscanning of a TV set. The desired amount of

underscan area, which is achieved through appropriate

scaling in the vertical and horizontal direction, can be filled

in the border generator with an arbitrary true colour tint.

7.10 Oscillator and Discrete Time Oscillator (DTO)

The master clock generation is realized as a 27 MHz

crystal oscillator, which can operate with either a

fundamental wave crystal or a 3rd-harmonic crystal.

The crystal clock supplies the DTO of the pixel clock

synthesizer, the video encoder and the I

C-bus control

block. It also usually supplies the triple DAC, with the

exception of the auxiliary VGA or HDTV mode, where the

triple DAC is clocked by the pixel clock (PIXCLK).

The DTO can be programmed to synthesize all relevant

pixel clock frequencies between circa 40 and 85 MHz.

Two programmable dividers provide the actual clock to be

used externally and internally. The dividers can be

programmed to factors of 1, 2, 4 and 8. For the internal

pixel clock, a divider ratio of 8 makes no sense and is thus

forbidden.

The internal clock can be switched completely to the pixel

clock input. In this event, the input FIFO is useless and will

be bypassed.

The entire pixel clock generation can be locked to the

vertical frequency. Both pixel clock dividers get

re-initialized every field. Optionally, the DTO can be

cleared with each V-sync. At proper programming, this will

make the pixel clock frequency a precise multiple of the

vertical and horizontal frequencies. This is required for

some graphic controllers.

7.11 Low-pass Clock Generation Circuit (CGC)

This block reduces the phase jitter of the synthesized pixel

clock. It works as a tracking filter for all relevant

synthesized pixel clock frequencies.

7.12 Encoder

7.12.1 VIDEO PATH

The encoder generates luminance and colour subcarrier

output signals from the Y, C

and C

baseband signals,

which are suitable for use as CVBS or separate Y and C

signals.

Input to the encoder, at 27 MHz clock (e.g. DVD), is either

originated from computer graphics at pixel clock, fed

through the FIFO and border generator, or a ITU-R BT.656

style signal.

2004 Mar 04 13

Philips Semiconductors Product speciﬁcation

Digital video encoder SAA7104H; SAA7105H

Luminance is modified in gain and in offset (the offset is

programmable in a certain range to enable different black

level set-ups). A blanking level can be set after insertion of

a fixed synchronization pulse tip level, in accordance with

standard composite synchronization schemes. Other

manipulations used for the Macrovision anti-taping

process, such as additional insertion of AGC super-white

pulses (programmable in height), are supported by the

SAA7104H only.

To enable easy analog post filtering, luminance is

interpolated from a 13.5 MHz data rate to a 27 MHz data

rate, thereby providing luminance in a 10-bit resolution.

The transfer characteristics of the luminance interpolation

filter are illustrated in Figs 6 and 7. Appropriate transients

at start/end of active video and for synchronization pulses

are ensured.

Chrominance is modified in gain (programmable

separately for C

and C

), and a standard dependent

burst is inserted, before baseband colour signals are

interpolated from a 6.75 MHz data rate to a 27 MHz data

rate. One of the interpolation stages can be bypassed,

thus providing a higher colour bandwidth, which can be

used for the Y and C output. The transfer characteristics of

the chrominance interpolation filter are illustrated in

Figs 4 and 5.

The amplitude (beginning and ending) of the inserted

burst, is programmable in a certain range that is suitable

for standard signals and for special effects. After the

succeeding quadrature modulator, colour is provided on

the subcarrier in 10-bit resolution.

The numeric ratio between the Y and C outputs is in

accordance with the standards.

7.12.2 TELETEXT INSERTION AND ENCODING (NOT

SIMULTANEOUSLY WITH REAL-TIME CONTROL)

Pin TTX_SRES receives a WST or NABTS teletext

bitstream sampled at the crystal clock. At each rising edge

of the output signal (TTXRQ) a single teletext bit has to be

provided after a programmable delay at input pin

TTX_SRES.

Phase variant interpolation is achieved on this bitstream in

the internal teletext encoder, providing sufficient small

phase jitter on the output text lines.

TTXRQ_XCLKO2 provides a fully programmable request

signal to the teletext source, indicating the insertion period

of bitstream at lines which can be selected independently

for both fields. The internal insertion window for text is set

to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS)

teletext bits including clock run-in bits. The protocol and

timing are illustrated in Fig.15.

Alternatively, this pin can be provided with a buffered

crystal clock (XCLK) of 13.5 MHz.

7.12.3 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING

Five bytes of VPS information can be loaded via the

C-bus and will be encoded in the appropriate format into

line 16.

7.12.4 CLOSED CAPTION ENCODER

Using this circuit, data in accordance with the specification

of Closed Caption or extended data service, delivered by

the control interface, can be encoded (line 21). Two

dedicated pairs of bytes (two bytes per field), each pair

preceded by run-in clocks and framing code, are possible.

The actual line number in which data is to be encoded, can

be modified in a certain range.

The data clock frequency is in accordance with the

definition for NTSC M standard 32 times horizontal line

frequency.

Data LOW at the output of the DACs corresponds to 0 IRE,

data HIGH at the output of the DACs corresponds to

approximately 50 IRE.

It is also possible to encode Closed Caption data for 50 Hz

field frequencies at 32 times the horizontal line frequency.

7.12.5 ANTI-TAPING (SAA7104H ONLY)

For more information contact your nearest Philips

Semiconductors sales office.

7.13 RGB processor

This block contains a dematrix in order to produce RED,

GREEN and BLUE signals to be fed to a SCART plug.

Before Y, C

and C

signals are de-matrixed, individual

gain adjustment for Y and colour difference signals and

2 times oversampling for luminance and 4 times

oversampling for colour difference signals is performed.

The transfer curves of luminance and colour difference

components of RGB are illustrated in Figs 8 and 9.

2004 Mar 04 14

Philips Semiconductors Product speciﬁcation

Digital video encoder SAA7104H; SAA7105H

7.14 Triple DAC

Both Y and C signals are converted from digital-to-analog

in a 10-bit resolution at the output of the video encoder.

Y and C signals are also combined into a 10-bit CVBS

signal.

The CVBS output signal occurs with the same processing

delay as the Y, C and optional RGB or C

-Y-C

outputs.

Absolute amplitude at the input of the DAC for CVBS is

reduced by

⁄

with respect to Y and C DACs to make

maximum use of the conversion ranges.

RED, GREEN and BLUE signals are also converted from

digital-to-analog, each providing a 10-bit resolution.

The reference currents of all three DACs can be adjusted

individually in order to adapt for different output signals.

In addition, all reference currents can be adjusted

commonly to compensate for small tolerances of the

on-chip band gap reference voltage.

Alternatively, all currents can be switched off to reduce

power dissipation.

All three outputs can be used to sense for an external load

(usually 75 Ω) during a pre-defined output. A flag in the

C-bus status byte reflects whether a load is applied or

not. In addition, an automatic sense mode can be

activated which indicates a 75 Ω load at any of the three

outputs at the dedicated interrupt pin TVD.

If the SAA7104H; SAA7105H is required to drive a second

(auxiliary) VGA monitor or an HDTV set, the DACs receive

the signal coming from the HD data path. In this event, the

DACs are clocked at the incoming PIXCLKI instead of the

27 MHz crystal clock used in the video encoder.

7.15 HD data path

This data path allows the SAA7104H; SAA7105H to be

used with VGA or HDTV monitors. It receives its data

directly from the cursor generator and supports RGB and

Y-P

-P

output formats (RGB not with Y-P

-P

input

formats). No scaling is done in this mode.

A gain adjustment either leads the full level swing to the

digital-to-analog converters or reduces the amplitude by a

factor of 0.69. This enables sync pulses to be added to the

signal as it is required for display units expecting signals

with sync pulses, either regular or 3-level syncs.

7.16 Timing generator

The synchronization of the SAA7104H; SAA7105H is able

to operate in two modes; slave mode and master mode.

In slave mode, the circuit accepts sync pulses on the

bidirectional FSVGC (frame sync), VSVGC (vertical sync)

and HSVGC (horizontal sync) pins: the polarities of the

signals can be programmed. The frame sync signal is only

necessary when the input signal is interlaced, in other

cases it may be omitted. If the frame sync signal is present,

it is possible to derive the vertical and the horizontal phase

from it by setting the HFS and VFS bits. HSVGC and

VSVGC are not necessary in this case, so it is possible to

switch the pins to output mode.

Alternatively, the device can be triggered by auxiliary

codes in a ITU-R BT.656 data stream via PD7 to PD0.

Only vertical frequencies of 50 and 60 Hz are allowed with

the SAA7104H; SAA7105H. In slave mode, it is not

possible to lock the encoders colour carrier to the line

frequency with the PHRES bits.

In the (more common) master mode, the time base of the

circuit is continuously free-running. The IC can output a

frame sync at pin FSVGC, a vertical sync at pin VSVGC, a

horizontal sync at pin HSVGC and a composite blanking

signal at pin CBO. All of these signals are defined in the

PIXCLK domain. The duration of HSVGC and VSVGC are

fixed, they are 64 clocks for HSVGC and 1 line for VSVGC.

The leading slopes are in phase and the polarities can be

programmed.

The input line length can be programmed. The field length

is always derived from the field length of the encoder and

the pixel clock frequency that is being used.

CBO acts as a data request signal. The circuit accepts

input data at a programmable number of clocks after CBO

goes active. This signal is programmable and it is possible

to adjust the following (see Figs 13 and 14):

• The horizontal offset

• The length of the active part of the line

• The distance from active start to first expected data

• The vertical offset separately for odd and even fields

• The number of lines per input field.

In most cases, the vertical offsets for odd and even fields

are equal. If they are not, then the even field will start later.

The SAA7104H; SAA7105H will also request the first input

lines in the even field, the total number of requested lines

will increase by the difference of the offsets.

As stated above, the circuit can be programmed to accept

the look-up and cursor data in the first 2 lines of each field.

The timing generator provides normal data request pulses

for these lines; the duration is the same as for regular lines.

2004 Mar 04 15

Philips Semiconductors Product speciﬁcation

Digital video encoder SAA7104H; SAA7105H

The additional request pulses will be suppressed with

LUTL set to logic 0; see Table 108. The other vertical

timings do not change in this case, so the first active line

can be number 2, counted from 0.

7.17 Pattern generator for HD sync pulses

The pattern generator provides appropriate

synchronization patterns for the video data path in

auxiliary monitor or HDTV mode. It provides maximum

flexibility in terms of raster generation for all interlaced and

non-interlaced computer graphics or ATSC formats. The

sync engine is capable of providing a combination of

event-value pairs which can be used to insert certain

values in the outgoing data stream at specified times.

It can also be used to generate digital signals associated

with time events. These can be used as digital horizontal

and vertical synchronization signals on pins HSM_CSYNC

and VSM.

The picture position is adjustable through the

programmable relationship between the sync pulses and

the video contents.

The generation of embedded analog sync pulses is bound

to a number of events which can be defined for a line.

Several of these line timing definitions can exist in parallel.

For the final sync raster composition a certain sequence of

lines with different sync event properties has to be defined.

The sequence specifies a series of line types and the

number of occurrences of this specific line type. Once the

sequence has been completed, it restarts from the

beginning. All pulse shapes are filtered internally in order

to avoid ringing after analog post filters.

The sequence of the generated pulse stream must fit

precisely to the incoming data stream in terms of the total

number of pixels per line and lines per frame.

The sync engines flexibility is achieved by using a

sequence of linked lists carrying the properties for the

image, the lines as well as fractions of lines. Figure 3

illustrates the context between the various tables.

The first table serves as an array to hold the correct

sequence of lines that compose the synchronization

raster; it can contain up to 16 entries. Each entry holds a

4-bit index to the next table and a 10-bit counter value

which specifies how often this particular line is invoked.

If the necessary line count for a particular line exceeds the

10 bits, it has to use two table entries.

The 4-bit index in the line count array points to the line type

array. It holds up to 15 entries (index 0 is not used),

index 1 points to the first entry, index 2 to the second entry

of the line type array etc.

Each entry of the line type array can hold up to 8 index

pointers to another table. These indices point to portions of

a line pulse pattern: A line could be split up e.g. into a sync,

a blank, and an active portion followed by another blank

portion, occupying four entries in one table line.

Each index of this table points to a particular line of the

next table in the linked list. This table is called the line

pattern array and each of the up to seven entries stores up

to four pairs of a duration in pixel clock cycles and an index

to a value table. The table entries are used to define

portions of a line representing a certain value for a certain

number of clock cycles.

The value specified in this table is actually another 3-bit

index into a value array which can hold up to eight 8-bit

values. If bit 4 (MSB) of the index is logic 1, the value is

inserted into the G or Y signal, only; if bit 4 = 0, the

associated value is inserted into all three signals.

Two additional bits of the entries in the value array (LSBs

of the second byte) determine if the associated events

appear as a digital pulse on the HSM_CSYNC and/or VSM

outputs.

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