MPC8640处理器家族技术规格详解

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"MPC8640硬件规格说明书概述了NXP Semiconductors的MPC8640和MPC8640D处理器，它们是集成的嵌入式主机处理器，适用于网络、存储、无线基础设施和通用嵌入式应用。处理器家族基于Power Architecture™ e600内核，MPC8640包含一个内核，而MPC8640D则包含两个。文档中详细介绍了这两个处理器的主要功能单元和特性，包括电气特性、电源特性、输入时钟、复位初始化、DDR和DDR2 SDRAM以及以太网等模块。" MPC8640系列处理器的核心特性在于它们对Power Architecture™ e600架构的集成。这个架构提供高性能计算能力，支持多线程处理，适合处理复杂的嵌入式系统任务。MPC8640单核心版本和MPC8640D双核心版本在设计上保持了一致性，但MPC8640D的双核配置允许更高的并行处理能力和更大的系统吞吐量。在电气特性方面，文档详细列出了处理器的工作电压、电流和其他电气参数，这对于系统设计者确保处理器在各种工作条件下稳定运行至关重要。这些参数通常会影响系统的功耗、散热设计和电源管理策略。电源特性部分讨论了处理器在不同工作模式下的功耗，包括活跃、空闲和深度睡眠模式，这对于优化能效和降低系统运行成本很有帮助。此外，还可能包含关于如何管理和监控电源状态的信息。输入时钟部分详细说明了处理器所需的时钟源，包括时钟频率、抖动要求和同步/异步时钟操作。这些信息对于系统时序设计和时钟树构建至关重要，确保处理器与其他组件的同步。复位初始化章节介绍了处理器在上电或复位后的行为，包括内部寄存器的初始状态、复位信号的类型和持续时间，这对于系统的可靠启动和故障恢复是必要的。 DDR和DDR2 SDRAM部分提供了关于内存接口的详细信息，包括内存控制器的特性、内存速度支持、地址和控制信号的时序，以及如何配置内存 bank以优化性能。这有助于设计者选择合适的内存模块和优化内存子系统的性能。最后，以太网部分涉及增强型以太网功能，可能包括高速连接、流控制、错误检测和校正机制，这些都是现代网络设备不可或缺的部分。这部分信息对于实现高效、可靠的网络连接至关重要。 MPC8640硬件规格说明书提供了全面的技术数据，对于设计和开发基于这些处理器的嵌入式系统来说，是宝贵的参考资源。它涵盖了从基本的硬件接口到高级功能的所有细节，帮助工程师实现最佳的系统性能和稳定性。

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 5

Input Clocks

NXP Semiconductors16

4.1.1 SYSCLK and Spread Spectrum Sources

Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference

emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise

magnitude in order to meet industry and government requirements. These clock sources intentionally add

long-term jitter to diffuse the EMI spectral content. The jitter specification given in Table 8 considers

short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter should meet the

MPC8640 input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns,

and the MPC8640 is compatible with spread spectrum sources if the recommendations listed in Table 9 are

observed.

It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies

must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is

operated at its maximum rated e600 core frequency should avoid violating the stated limits by using

down-spreading only.

SYSCLK rise and fall time t

, t

0.6 1.0 1.2 ns 2

SYSCLK duty cycle t

KHK

SYSCLK

40 — 60 % 3

SYSCLK jitter — — — 150 ps 4, 5

Notes:

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3, “e600 to MPX clock PLL

Ratio,” for ratio settings.

2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the short term jitter only and is guaranteed by design.

5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow

cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. Note that the frequency modulation

for SYSCLK reduces significantly for the spread spectrum source case. This is to guarantee what is supported based on

design.

Table 9. Spread Spectrum Clock Source Recommendations

At recommended operating conditions. See Ta bl e 2.

Parameter Min Max Unit Notes

Frequency modulation — 50 kHz 1

Frequency spread — 1.0 % 1, 2

Notes:

1. Guaranteed by design.

2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the

minimum and maximum specifications given in Ta bl e 8 .

Table 8. SYSCLK AC Timing Specifications (continued)

At recommended operating conditions (see Ta bl e 2 ) with OV

= 3.3 V ± 165 mV.

Parameter Symbol Min Typical Max Unit Notes

Input Clocks

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 5

NXP Semiconductors 17

SDn_REF_CLK and SDn_REF_CLK were designed to work with a spread spectrum clock (+0 to 0.5%

spreading at 30-33 kHz rate is allowed), assuming both ends have same reference clock. For better results,

use a source without significant unintended modulation.

4.2 Real Time Clock Timing

The RTC input is sampled by the platform clock (MPX clock). The output of the sampling latch is then

used as an input to the counters of the PIC. There is no jitter specification. The minimum pulse width of

the RTC signal should be greater than 2 the period of the MPX clock. That is, minimum clock high time

is 2  t

MPX

, and minimum clock low time is 2  t

MPX

. There is no minimum RTC frequency; RTC may be

grounded if not needed.

4.3 eTSEC Gigabit Reference Clock Timing

Table 10 provides the eTSEC gigabit reference clocks (EC1_GTX_CLK125 and EC2_GTX_CLK125)

AC timing specifications for the MPC8640.

NOTE

The phase between the output clocks TSEC1_GTX_CLK and

TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase

between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK

(ports 3 and 4) is no more than 100 ps.

4.4 Platform Frequency Requirements for PCI-Express and Serial

RapidIO

The MPX platform clock frequency must be considered for proper operation of the high-speed PCI

Express and Serial RapidIO interfaces as described below.

For proper PCI Express operation, the MPX clock frequency must be greater than or equal to:

Table 10. ECn_GTX_CLK125 AC Timing Specifications

Parameter Symbol Min Typical Max Unit Notes

ECn_GTX_CLK125 frequency f

G125

— 125 ± 100

ppm

—MHz3

ECn_GTX_CLK125 cycle time t

G125

—8—ns—

ECn_GTX_CLK125 peak-to-peak jitter t

G125J

— — 250 ps 1

ECn_GTX_CLK125 duty cycle

GMII, TBI

1000Base-T for RGMII, RTBI

G125H

G125

—

%1, 2

Notes:

1. Timing is guaranteed by design and characterization.

2. ECn_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. ECn_GTX_CLK125

duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC

GTX_CLK. See Section 8.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and 100Base-T

reference clock.

3. ±100 ppm tolerance on ECn_GTX_CLK125 frequency.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 5

RESET Initialization

NXP Semiconductors18

527 MHz x (PCI-Express link width)

16 / (1 + cfg_plat_freq)

Note that at MPX = 400 MHz, cfg_plat_freq = 0 and at MPX > 400 MHz, cfg_plat_freq = 1. Therefore,

when operating PCI Express in x8 link width, the MPX platform frequency must be 400 MHz with

cfg_plat_freq = 0 or greater than or equal to 527 MHz with cfg_plat_freq = 1.

For proper Serial RapidIO operation, the MPX clock frequency must be greater than or equal to:

2 × (0.8512) × (Serial RapidIO interface frequency) × (Serial RapidIO link width)

4.5 Other Input Clocks

For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,

see the specific section of this document.

5 RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the MPC8640. Table 11 provides the RESET initialization AC timing specifications.

Table 12 provides the PLL lock times.

Table 11. RESET Initialization Timing Specifications

Parameter Min Max Unit Notes

Required assertion time of HRESET

100 — s—

Minimum assertion time for SRESET

_0 & SRESET_1 3 — SYSCLKs 1

Platform PLL input setup time with stable SYSCLK before HRESET

negation

100 — s2

Input setup time for POR configs (other than PLL config) with respect to

negation of HRESET

4 — SYSCLKs 1

Input hold time for all POR configs (including PLL config) with respect to

negation of HRESET

2 — SYSCLKs 1

Maximum valid-to-high impedance time for actively driven POR configs

with respect to negation of HRESET

— 5 SYSCLKs 1

Notes:

1. SYSCLK is the primary clock input for the MPC8640.

2 This is related to HRESET

assertion time. Stable PLL configuration inputs are required when a stable SYSCLK is applied. See

the MPC8641D Integrated Host Processor Reference Manual for more details on the power-on reset sequence.

Table 12. PLL Lock Times

Parameter Min Max Unit Notes

(Platform and E600) PLL lock times — 100 s1

Local bus PLL — 50 s—

Notes:

1.The PLL lock time for e600 PLLs require an additional 255 MPX_CLK cycles.

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