![](https://csdnimg.cn/release/download_crawler_static/87793738/bg3.jpg)
input clk,k1,k2;
output reg k;
reg[3:0] qc;
reg rc;
always@(posedge clk)
begin qc=qc+1;
if(qc<8) rc=0;
else rc=1;
case({k1,k2})
0:k=rc;
1:k=0;
2:k=1;
3:k=rc;
endcase
end
Endmodule
闹钟
module naozhong(s,f,led,zt);
input zt;
input[7:0]s,f;
output led;
reg led;
always
begin
if(s=='h06&&f=='h01)
led=1;
else
led=0;
if(zt==1)led=0;
end
endmodule
按键调节端口