STM32G070CBKBRB单片机错误修复与描述

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"STM32G070CBKBRB单片机的勘误手册_ENV1.pdf" 是一份关于STM32G070CB/KB/RB系列微控制器的文档，它提供了这些设备存在的错误和限制的总结与描述。这份手册针对的是STM32G070CB/KB/RB的部分编号以及指定的设备变体，并且与设备数据表和参考手册RM0454中的信息进行了对比。文档中提到的"设备误差"是指实际设备行为与预期设备行为之间的偏差，这被视为设备的限制。而参考手册或数据表中的描述与预期设备行为不一致，则被认为是文档错误，统称为"errata"，涵盖了设备限制和文档错误两个方面。在"Applicability"部分，该文档明确了适用范围，即适用于STM32G070CB/KB/RB系列的特定部件编号和设备变体。文档详细列出了硅片修订代码（Silicon revision codes）和设备标记（Device marking），如STM32G070CB/KB/RB的B版本，其REV_ID字段在DBGMCU_IDCODE寄存器的REV_ID[15:0]位字段中可以找到。表格1提供了不同设备变体的参考，包括硅片修订代码和设备标记。例如，STM32G070CB/KB/RB的初始版本标记为B，REV_ID为0x20001。用户可以通过数据表来识别不同封装类型上的此代码。 STM32G070CB/KB/RB的错误表（Erratasheet）列出了设备的限制情况，如ES0468-Rev1-November2018，这是一个快速参考，详细列举了STM32G070CB/KB/RB设备的限制问题。对于更详细的信息，用户被建议联系当地的意法半导体销售办公室或者访问官方网站www.st.com获取支持。这份勘误手册对于开发者来说是至关重要的，因为它可以帮助他们理解STM32G070CB/KB/RB系列的实际性能和可能存在的问题，从而在设计过程中做出适当的调整和优化，确保系统的稳定性和可靠性。

2 Description of device errata

The following sections describe limitations of the applicable devices with Arm

core and provide workarounds if

available. They are grouped by device functions.

Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

2.1 Core

Errata notice for the Arm

Cortex

-M0+ core revision r0p1 is available from http://infocenter.arm.com.

2.2 System

2.2.1 Unstable LSI when it clocks RTC or CSS on LSE

Description

The LSI clock can become unstable (duty cycle different from 50 %) and its maximum frequency can become

significantly higher than 32 kHz, when:

• LSI clocks the RTC, or it clocks the clock security system (CSS) on LSE (which holds when the LSECSSON

bit set), and

• the V

power domain is reset while the backup domain is not reset, which happens:

– upon exiting Shutdown mode

– if V

BAT

is separate from V

and V

goes off then on

– if V

BAT

is tied to V

(internally in the package for products not featuring the VBAT pin, or externally)

and a short (< 1 ms) V

drop under V

(min) occurs

Workaround

Apply one of the following measures:

• Clock the RTC with LSE or HSE/32, without using the CSS on LSE

• If LSI clocks the RTC or when the LSECSSON bit is set, reset the backup domain upon each V

power up

(when the BORRSTF flag is set). If V

BAT

is separate from V

, also restore the RTC configuration, backup

registers and anti-tampering configuration.

2.2.2 WUFx wakeup flag wrongly set during configuration

Description

Upon configuring a wakeup pin (WKUPx), the corresponding wakeup flag (WUFx) might spuriously go high

depending on the state and configuration of the wakeup pin.

Workaround

After configuring a wakeup pin, clear its corresponding WUFx flag.

2.2.3 Under Level 1 read protection, booting from Main Flash memory selected through PA14‑BOOT0

pin is not functional

Description

With the Flash memory read protection set to Level 1 and the boot mode selected through the PA14-BOOT0 pin

(BOOT0 function of the pin), an attempt to boot from Main Flash memory can wrongly be interpreted by the read

protection mechanism as an unauthorized access, preventing the user code execution. Booting from Main Flash

memory operates correctly if selected through option bits (nBOOT_SEL and nBOOT0 both set).

STM32G070CB/KB/RB

Description of device errata

ES0468 - Rev 1

page 3/11

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