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首页Atheros AR9344: 2x2 IEEE802.11n SoC 技术数据详解
Atheros AR9344: 2x2 IEEE802.11n SoC 技术数据详解
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更新于2024-07-20
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"AR9344是一款由Atheros Communications公司设计的高度集成和功能丰富的IEEE 802.11n 2x2 2.4/5GHz高端无线局域网(WLAN)系统级芯片(SoC)。"
本文档主要介绍了AR9344芯片的技术规格和特性,它是一款在2010年由Atheros Communications推出的无线通信解决方案。AR9344芯片设计用于高级WLAN平台,旨在提供高性能的无线连接,支持2.4GHz和5GHz双频段,符合802.11n标准,可以实现高效的2x2 MIMO(多输入多输出)技术,显著提升了无线网络的吞吐量和稳定性。
AR9344芯片集成了MIPS微处理器架构,这使得该芯片不仅能够处理无线通信任务,还能够处理更复杂的计算和应用需求。此外,它还包括了如信号增强技术(如Atheros的Signal-Sustain Technology™)等专有技术,这些技术有助于提高无线信号的质量和覆盖范围,确保在网络环境中提供可靠的连接。
这款SoC还包含了一系列高级功能,例如安装和配置的简便性(可能通过InstallNGo™技术实现),以及可能用于设备管理和用户友好的特性,如U-Map™和U-Tag™。这些特性使得AR9344芯片非常适合于需要高效、稳定和用户友好无线体验的设备,如路由器、接入点和无线网卡。
Atheros Communications的AR9344芯片的推出,是其推动无线未来战略的一部分,如SuperG®、SuperN®等技术,表明了Atheros致力于提供高速、低干扰的无线解决方案。值得注意的是,此数据表是初步版本,可能随着产品的进一步开发和改进而发生变化。
总结来说,AR9344是一款针对高级WLAN平台设计的高性能无线SoC,集成了先进的无线技术、强大的处理能力以及一系列优化用户体验的特性,为家庭和企业环境提供了强大且稳定的无线网络连接。
PRELIMINARY
16 • AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC Atheros Communications, Inc.
16 • December 2010 COMPANY CONFIDENTIAL
8.19.19 Checksum Burst Control
(ARB_BURST) ...........................298
8.19.20 DMA Reset (RESET_DMA) ... 298
8.19.21 Checksum Configuration
(CONFIG) ..................................298
8.20 UART1 (High-Speed) Registers ........ 299
8.20.1 UART1 Transmit and Rx FIFO
Interface (UART1_DATA) .......299
8.20.2 UART1 Configuration and Status
(UART1_CS) ..............................300
8.20.3 UART1 Clock (UART1_CLOCK) .
301
8.20.4 UART1 Interrupt/Control Status
(UART1_INT) ............................301
8.20.5 UART1 Interrupt Enable
(UART1_INT_EN) ....................302
8.21 GMAC0/GMAC1 Registers ..............303
8.21.1 MAC Configuration 1 ..............308
8.21.2 MAC Configuration 2 ..............309
8.21.3 IPG/IFG .....................................309
8.21.4 Half-Duplex ...............................310
8.21.5 Maximum Frame Length ......... 310
8.21.6 MII Configuration .....................311
8.21.7 MII Command ...........................311
8.21.8 MII Address ...............................312
8.21.9 MII Control ................................312
8.21.10 MII Status .................................312
8.21.11 MII Indicators ..........................312
8.21.12 Interface Control .....................313
8.21.13 Interface Status ........................314
8.21.14 STA Address 1 .........................315
8.21.15 STA Address 2 .........................315
8.21.16 ETH_FIFO RAM Configuration 0
316
8.21.17 ETH Configuration 1 .............. 317
8.21.18 ETH Configuration 2 .............. 317
8.21.19 ETH Configuration 3 .............. 317
8.21.20 ETH Configuration 4 .............. 318
8.21.21 ETH Configuration 5 .............. 318
8.21.22 Tx/Rx 64 Byte Frame Counter
(TR64) .........................................319
8.21.23 Tx/Rx 65-127 Byte Frame Counter
(TR127) .......................................319
8.21.24 Tx/Rx 128-255 Byte Frame
Counter (TR255) ........................319
8.21.25 Tx/Rx 256-511 Byte Frame
Counter (TR511) ........................ 319
8.21.26 Tx/Rx 512-1023 Byte Frame
Counter (TR1K) ......................... 320
8.21.27 Tx/Rx 1024-1518 Byte Frame
Counter (TRMAX) .................... 320
8.21.28 Tx/Rx 1519-1522 Byte VLAN
Frame Counter (TRMGV) ........ 320
8.21.29 Receive Byte Counter (RXBT) 320
8.21.30 Receive Packet Counter (RPKT) .
321
8.21.31 Receive FCS Error Counter (RFCS)
321
8.21.32 Receive Multicast Packet Counter
(RMCA) ...................................... 321
8.21.33 Receive Broadcast Packet Counter
(RBCA) ....................................... 321
8.21.34 Receive Control Frame Packet
Counter (RXCF) ........................ 322
8.21.35 Receive Pause Frame Packet
Counter (RXPF) ......................... 322
8.21.36 Receive Unknown OPCode Packet
Counter (RXUO) ....................... 322
8.21.37 Receive Alignment Error Counter
(RALN) ....................................... 322
8.21.38 Receive Frame Length Error
Counter (RFLR) ......................... 323
8.21.39 Receive Code Error Counter
(RCDE) ....................................... 323
8.21.40 Receive Carrier Sense Error
Counter (RCSE) ......................... 323
8.21.41 Receive Undersize Packet Counter
(RUND) ...................................... 323
8.21.42 Receive Oversize Packet Counter
(ROVR) ....................................... 324
8.21.43 Receive Fragments Counter
(RFRG) ........................................ 324
8.21.44 Receive Jabber Counter (RJBR) 324
8.21.45 Receive Dropped Packet Counter
(RDRP) ....................................... 324
8.21.46 Transmit Byte Counter (TXBT) 325
8.21.47 Transmit Packet Counter (TPKT)
325
8.21.48 Transmit Multicast Packet Counter
(TMCA) ...................................... 325
8.21.49 Transmit Broadcast Packet
Counter (TBCA) ........................ 325
8.21.50 Transmit Pause Control Frame
Counter (TXPF) ......................... 326
PRELIMINARY
Atheros Communications, Inc. AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC • 17
COMPANY CONFIDENTIAL December 2010 • 17
8.21.51 Transmit Deferral Packet Counter
(TDFR) ........................................ 326
8.21.52 Transmit Excessive Deferral Packet
Counter (TEDF) .........................326
8.21.53 Transmit Single Collision Packet
Counter (TSCL) .........................326
8.21.54 Transmit Multiple Collision Packet
(TMCL) .......................................327
8.21.55 Transmit Late Collision Packet
Counter (TLCL) .........................327
8.21.56 Transmit Excessive Collision
Packet Counter (TXCL) ............327
8.21.57 Transmit Total Collision Counter
(TNCL) .......................................327
8.21.58 Transmit Pause Frames Honored
Counter (TPFH) ........................328
8.21.59 Transmit Drop Frame Counter
(TDRP) ........................................ 328
8.21.60 Transmit Jabber Frame Counter
(TJBR) ......................................... 328
8.21.61 Transmit FCS Error Counter
(TFCS) ......................................... 328
8.21.62 Transmit Control Frame Counter
(TXCF) ........................................ 329
8.21.63 Transmit Oversize Frame Counter
(TOVR) .......................................329
8.21.64 Transmit Undersize Frame
Counter (TUND) .......................329
8.21.65 Transmit Fragment Counter
(TFRG) ........................................ 329
8.21.66 Carry Register 1 (CAR1) ........330
8.21.67 Carry Register 2 (CAR2) ........331
8.21.68 Carry Mask Register 1 (CAM1) ...
332
8.21.69 Carry Mask Register 2 (CAM2) ...
333
8.21.70 DMA Transfer Control for Queue 0
(DMATXCNTRL_Q0) .............. 333
8.21.71 Descriptor Address for Queue 0 Tx
(DMATXDESCR_Q0) ............... 334
8.21.72 Transmit Status
(DMATXSTATUS) ....................334
8.21.73 Receive Control (DMARXCTRL)
334
8.21.74 Pointer to Receive Descriptor
(DMARXDESCR) ......................335
8.21.75 Receive Status (DMARXSTATUS)
335
8.21.76 Interrupt Mask
(DMAINTRMASK) .................. 336
8.21.77 Interrupts (DMAINTERRUPT) 337
8.21.78 Ethernet TX Burst
(ETH_ARB_TX_BURST) .......... 337
8.21.79 Current Tx and Rx FIFO Depth
(ETH_XFIFO_DEPTH) ............. 338
8.21.80 Ethernet Transmit FIFO
Throughput (ETH_TXFIFO_TH) .
338
8.21.81 Ethernet Receive FIFO Threshold
(ETH_RXFIFO_TH) .................. 338
8.21.82 Ethernet Free Timer
(ETH_FREE_TIMER) ............... 339
8.21.83 DMA Transfer Control for Queue 1
(DMATXCNTRL_Q1) .............. 339
8.21.84 Descriptor Address for Queue 1 Tx
(DMATXDESCR_Q1) ............... 339
8.21.85 DMA Transfer Control for Queue 2
(DMATXCNTRL_Q2) .............. 339
8.21.86 Descriptor Address for Queue 2 Tx
(DMATXDESCR_Q2) ............... 340
8.21.87 DMA Transfer Control for Queue 3
(DMATXCNTRL_Q3) .............. 340
8.21.88 Descriptor Address for Queue 3 Tx
(DMATXDESCR_Q3) ............... 340
8.21.89 DMA Transfer Arbitration
Configuration (DMATXARBCFG)
340
8.21.90 Tx Status and Packet Count for
Queues 1 to 3
(DMATXSTATUS_123) ............ 341
8.21.91 Local MAC Address Dword0
(LCL_MAC_ADDR_DW0) ...... 341
8.21.92 Local MAC Address Dword1
(LCL_MAC_ADDR_DW1) ...... 341
8.21.93 Next Hop Router MAC Address
Dword0
(NXT_HOP_DST_ADDR_DW0) ..
341
8.21.94 Next Hop Router MAC
Destination Address Dword1
(NXT_HOP_DST_ADDR_DW1) ..
342
8.21.95 Local Global IP Address 0
(GLOBAL_IP_ADDR0) ............ 342
8.21.96 Local Global IP Address 1
(GLOBAL_IP_ADDR1) ............ 342
PRELIMINARY
18 • AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC Atheros Communications, Inc.
18 • December 2010 COMPANY CONFIDENTIAL
8.21.97 Local Global IP Address 2
(GLOBAL_IP_ADDR2) ............342
8.21.98 Local Global IP Address 3
(GLOBAL_IP_ADDR3) ............342
8.21.99 Egress NAT Control and Status
(EG_NAT_CSR) ........................343
8.21.100 Egress NAT Counter
(EG_NAT_CNTR) .....................343
8.21.101 Ingress NAT Control and Status
(IG_NAT_CSR) ..........................344
8.21.102 Ingress NAT Counter
(IG_NAT_CNTR) ......................344
8.21.103 Egress ACL Control and Status
(EG_ACL_CSR) .........................345
8.21.104 Ingress ACL Control and Status
(IG_ACL_CSR) ..........................345
8.21.105 Egress ACL CMD0 and Action
(EG_ACL_CMD0_AND_ACTION)
345
8.21.106 Egress ACL CMD1, CMD2,
CMD3 and CMD4
(EG_ACL_CMD1234) ...............346
8.21.107 Egress ACL OPERAND 0
(EG_ACL_OPERAND0) ..........346
8.21.108 Egress ACL OPERAND 1
(EG_ACL_OPERAND1) ..........346
8.21.109 Egress ACL Memory Control
(EG_ACL_MEM_CONTROL) . 347
8.21.110 Ingress ACL CMD0 and Action
(IG_ACL_CMD0_AND_ACTION)
348
8.21.111 Ingress ACL CMD1, CMD2,
CMD3 and CMD4
(IG_ACL_CMD1234) ................348
8.21.112 Ingress ACL OPERAND 0
(IG_ACL_OPERAND0) ...........348
8.21.113 Ingress ACL OPERAND 1
(IG_ACL_OPERAND1) ...........349
8.21.114 Ingress ACL Memory Control
(IG_ACL_MEM_CONTROL) .. 349
8.21.115 Ingress ACL Counter Group 0
(IG_ACL_COUNTER_GRP0) ..350
8.21.116 Ingress ACL Counter Group 1
(IG_ACL_COUNTER_GRP1) ..350
8.21.117 Ingress ACL Counter Group 2
(IG_ACL_COUNTER_GRP2) ..350
8.21.118 Ingress ACL Counter Group 3
(IG_ACL_COUNTER_GRP3) ..350
8.21.119 Ingress ACL Counter Group 4
(IG_ACL_COUNTER_GRP4) . 351
8.21.120 Ingress ACL Counter Group 5
(IG_ACL_COUNTER_GRP5) . 351
8.21.121 Ingress ACL Counter Group 6
(IG_ACL_COUNTER_GRP6) . 351
8.21.122 Ingress ACL Counter Group 7
(IG_ACL_COUNTER_GRP7) . 351
8.21.123 Ingress ACL Counter Group 8
(IG_ACL_COUNTER_GRP8) . 352
8.21.124 Ingress ACL Counter Group 9
(IG_ACL_COUNTER_GRP9) . 352
8.21.125 Ingress ACL Counter Group 10
(IG_ACL_COUNTER_GRP10) 352
8.21.126 Ingress ACL Counter Group 11
(IG_ACL_COUNTER_GRP11) 352
8.21.127 Ingress ACL Counter Group 12
(IG_ACL_COUNTER_GRP12) 353
8.21.128 Ingress ACL Counter Group 13
(IG_ACL_COUNTER_GRP13) 353
8.21.129 Ingress ACL Counter Group 14
(IG_ACL_COUNTER_GRP14) 353
8.21.130 Ingress ACL Counter Group 15
(IG_ACL_COUNTER_GRP15) 353
8.21.131 Egress ACL Counter Group 0
(EG_ACL_COUNTER_GRP0) 354
8.21.132 Egress ACL Counter Group 1
(EG_ACL_COUNTER_GRP1) 354
8.21.133 Egress ACL Counter Group 2
(EG_ACL_COUNTER_GRP2) 354
8.21.134 Egress ACL Counter Group 3
(EG_ACL_COUNTER_GRP3) 354
8.21.135 Egress ACL Counter Group 4
(EG_ACL_COUNTER_GRP4) 355
8.21.136 Egress ACL Counter Group 5
(EG_ACL_COUNTER_GRP5) 355
8.21.137 Egress ACL Counter Group 6
(EG_ACL_COUNTER_GRP6) 355
8.21.138 Egress ACL Counter Group 7
(EG_ACL_COUNTER_GRP7) 355
8.21.139 Egress ACL Counter Group 8
(EG_ACL_COUNTER_GRP8) 356
8.21.140 Egress ACL Counter Group 9
(EG_ACL_COUNTER_GRP9) 356
8.21.141 Egress ACL Counter Group 10
(EG_ACL_COUNTER_GRP10) 356
8.21.142 Egress ACL Counter Group 11
(EG_ACL_COUNTER_GRP11) 356
PRELIMINARY
Atheros Communications, Inc. AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC • 19
COMPANY CONFIDENTIAL December 2010 • 19
8.21.143 Egress ACL Counter Group 12
(EG_ACL_COUNTER_GRP12) 357
8.21.144 Egress ACL Counter Group 13
(EG_ACL_COUNTER_GRP13) 357
8.21.145 Egress ACL Counter Group 14
(EG_ACL_COUNTER_GRP14) 357
8.21.146 Egress ACL Counter Group 15
(EG_ACL_COUNTER_GRP15) 357
8.21.147 Clear ACL Counters
(CLEAR_ACL_COUNTERS) .. 358
8.22 USB Controller Registers ...................358
8.22.1 Identification (ID) ..................... 360
8.22.2 General Hardware Parameters
(HWGENERAL) ........................360
8.22.3 Host Hardware Parameters
(HWHOST) ................................360
8.22.4 Device Hardware Parameters
(HWDEVICE) ............................ 361
8.22.5 Tx Buffer Hardware Parameters
(HWTXBUF) .............................. 361
8.22.6 Rx Buffer Hardware Parameters
(HWRXBUF) .............................. 361
8.22.7 General Purpose Timer 0 Load
(GPTIMER0LD) .........................361
8.22.8 General Purpose Timer 0 Control
(GPTIMER0CTRL) ....................362
8.22.9 General Purpose Timer 1 Load
(GPTIMER1LD) .........................362
8.22.10 General Purpose Timer 1 Control
(GPTIMER1CTRL) ....................363
8.22.11 Capability Register Length
(CAPLENGTH) .........................363
8.22.12 Host Interface Version Number
(HCIVERSION) .........................364
8.22.13 Host Control Structural
Parameters (HCSPARAMS) ....364
8.22.14 Host Control Capability
Parameters (HCCPARAMS) ... 365
8.22.15 Device Interface Version Number
(DCIVERSION) .........................365
8.22.16 Device Control Capability
Parameters (DCCPARAMS) ...365
8.22.17 USB Command (USBCMD) ... 366
8.22.18 USB Status (USBSTS) ..............368
8.22.19 USB Interrupt Enable (USBINTR)
370
8.22.20 USB Frame Index (FRINDEX) 372
8.22.21 Frame List Base Address
(PERIODICLISTBASE) ............ 373
8.22.22 USB Device Address
(DEVICEADDR) ....................... 373
8.22.23 Next Asynchronous List Address
(ASYNCLISTADDR) ................ 373
8.22.24 Address at Endpointlist in
Memory
(ENEDPOINTLIST_ADDR) .... 374
8.22.25 TT Status and Control (TTCTRL)
374
8.22.26 Programmable Burst Size
(BURSTSIZE) ............................. 374
8.22.27 Host Tx Pre-Buffer Packet Tuning
(TXFILLTUNING) .................... 375
8.22.28 Endpoint NAK (ENDPTNAK) 376
8.22.29 Endpoint NAK Enable
(ENDPTNAKEN) ..................... 376
8.22.30 Port/Status Control (PORTSC0)
377
8.22.31 USB Mode (USBMODE) ........ 382
8.22.32 Endpoint Setup Status
(ENDPTSETUPSTAT) .............. 383
8.22.33 Endpoint Initialization
(ENDPTPRIME) ........................ 383
8.22.34 Endpoint De-Initialization
(ENDPTFLUSH) ....................... 384
8.22.35 Endpoint Status
(ENDPTSTATUS) ..................... 384
8.22.36 Endpoint Complete
(ENDPTCOMPLETE) .............. 385
8.22.37 Endpoint Control 0
(ENDPTCTRL0) ........................ 385
8.22.38 Endpoint Control 1
(ENDPTCTRL1) ........................ 386
8.23 NAND Flash Registers ....................... 387
8.23.1 Controller Commands
(COMMAND) ........................... 388
8.23.2 Main Configuration (CONTROL)
389
8.23.3 Controller Status (STATUS) .... 391
8.23.4 Interrupt Mask (INT_MASK) . 392
8.23.5 Interrupt Status (INT_STATUS) 392
8.23.6 Configuration Parameters for the
ECC Module (ECC_CTRL) ...... 393
8.23.7 ECC Offset Value (ECC_OFFSET)
393
PRELIMINARY
20 • AR9344 Highly-Integrated 802.11n 2x2 2.4/5 GHz Premium SoC Atheros Communications, Inc.
20 • December 2010 COMPANY CONFIDENTIAL
8.23.8 Most Significant Part of the Address
Register 0/1 (ADDR0_0, ADDR0_1,
ADDR1_0, ADDR1_1) ..............394
8.23.9 NAND Flash Spare Area Size
(SPARE_SIZE) ...........................395
8.23.10 Hardware Protect Against the
Write/Erase Process Control
(PROTECT) ................................395
8.23.11 Enables Look-Up Register During
NAND Flash Memory Address
(LOOKUP_EN) .........................396
8.23.12 Lookup Table [7:0]
(LOOKUP[7:0]) ..........................396
8.23.13 DMA Module Base Address
(DMA_ADDR) ..........................397
8.23.14 DMA Module Counters Initial
Value (DMA_CNT) ..................397
8.23.15 DMA Module Control
(DMA_CTRL) ............................397
8.23.16 Memory Device Control
(MEM_CTRL) ............................398
8.23.17 Custom Page Size Value
(DATA_SIZE) ............................398
8.23.18 Read Status Command Output
Value (READ_STATUS) ..........398
8.23.19 Command Sequence Timings
Configuration (TIME_SEQ) ..... 399
8.23.20 Timing Configuration 0
(TIMING_ASYN) ......................399
8.23.21 Timing Configuration 1
(TIMING_SYN) .........................399
8.23.22 FIFO Module Interface
(FIFO_DATA) ............................400
8.23.23 DQS Signal Delay Effect
(TIME_MODE) ..........................400
8.23.24 DMA Module Address Offset
(DMA_ADDR_OFFSET) ..........400
8.23.25 Control for the FIFO Module
(FIFO_INIT) ...............................401
8.23.26 Configuration for the Two Generic
Sequences (GENERIC_SEQ_CTRL)
401
8.24 PCIE EP DMA Registers ....................402
8.24.1 Rx Descriptor Start Address
(RX_DESC_START_ADDRESS) 403
8.24.2 Rx DMA Start (RX_DMA_START)
403
8.24.3 Rx AHB Burst Size
(RX_BURST_SIZE) .................... 403
8.24.4 Packet Offset (PKT_OFFSET) . 404
8.24.5 Checksum (CHECKSUM) ....... 404
8.24.6 Rx Data Swap (RX_DATA_SWAP)
404
8.24.7 Tx Descriptor Start Address
(TX_DESC_START_ADDRESS) 405
8.24.8 Tx DMA Start (TX_DMA_START)
405
8.24.9 Interrupt Limit
(INTERRUPT_LIMIT) .............. 405
8.24.10 Tx AHB Burst Size
(TX_BURST_SIZE) .................... 406
8.24.11 Tx Data Swap (TX_DATA_SWAP)
406
8.24.12 Interrupt Status
(HOST_DMA_INTERRUPT) .. 407
8.24.13 Interrupt Mask
(HOST_DMA_INTERRUPT_MASK
) .................................................... 408
8.24.14 Arbitration Priority (PRIORITY)
408
8.25 Serial Flash SPI Controller Registers 409
8.25.1 SPI Controller GPIO Mode Select
(FUNCTION_SELECT_ADDR) 409
8.25.2 SPI Address Control
(SPI_CONTROL_ADDR) ........ 409
8.25.3 SPI I/O Address Control
(SPI_IO_CONTROL_ADDR) .. 410
8.25.4 SPI Read Data Address
(SPI_READ_DATA_ADDR) ... 410
8.25.5 SPI Data to Shift Out
(SPI_SHIFT_DATAOUT_ADDR)
410
8.25.6 SPI Content to Shift Out or In
(SPI_SHIFT_CNT_ADDR) ...... 411
8.25.7 SPI Data to Shift In
(SPI_SHIFT_DATAIN_ADDR) 411
8.26 Global Control Registers .................... 412
8.26.1 Mask Control ............................. 413
8.26.2 Operational Mode 0 ................. 413
8.26.3 Operational Mode 1 ................. 413
8.26.4 Global Interrupt ........................ 414
8.26.5 Global Interrupt Mask ............. 415
8.26.6 Global MAC Address .............. 415
8.26.7 Loop Check Result ................... 416
8.26.8 Flood Mask ................................ 416
剩余465页未读,继续阅读
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