AR9287单芯片2x2 MIMO Wi-Fi解决方案数据手册

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AR9287

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高通AR9287是一款专为2.4GHz 802.11n标准设计的单芯片解决方案，它集成了MAC（Media Access Control）、基带（BB）和无线射频功能，支持2x2 MIMO（Multiple-Input Multiple-Output）技术。这款芯片旨在满足高性能需求的应用场景，特别是那些需要强大链接稳定性的应用，如无线路由器、移动设备或物联网设备等。该芯片的核心特点是其集成度高，通过PCIe（Peripheral Component Interconnect Express）接口提供高速通信，以确保数据传输的高效性和可靠性。AR9287支持802.11n标准，这是一种无线局域网（WLAN）标准，设计目的是在2.4GHz频段实现更高的数据传输速率和更大的网络容量，通过MIMO技术允许多个数据流同时传输，从而显著提升无线连接性能。 AR9287具备以下主要特性： 1. **MIMO技术**: 提供双路天线配置，允许数据在两个空间维度上同时发送和接收，提高了数据吞吐量和抗干扰能力。 2. **高性能**: 2x2 MIMO架构能够处理多个并发连接，增强无线网络的并发用户数量，适合密集用户环境。 3. **PCIe接口**: 与传统的USB或SPI接口相比，PCIe提供了更快的数据传输速度，有助于减少延迟，提高整体系统响应速度。 4. **802.11n支持**: 采用最新的Wi-Fi标准，能够达到较高的理论最高速率，满足高清视频流、在线游戏和大数据传输的需求。 5. **Robust Link**: 为了确保稳定的连接，AR9287可能包括了自适应调制编码（AMC）、错误检测和校正机制，以及动态频率选择（DFS）等功能。 6. **品牌与商标**: Atheros是该芯片的主要制造商，拥有多项注册商标，如Atheros SST（Signal-Sustain Technology）、Ethos等，反映了其在无线通信领域的技术实力和创新。 AR9287数据手册详细介绍了芯片的电气特性和操作规范，以及如何将其集成到系统设计中，包括电源管理、接口配置、软件驱动和硬件兼容性等方面的信息。对于开发人员和系统设计师来说，这份手册是理解和优化AR9287性能、实现无线网络最佳效能的重要参考资料。

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12 • AR9287 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs Atheros Communications, Inc.

12 • February 2010 COMPANY CONFIDENTIAL

3.3 Descriptor Format

The transmit (Tx) descriptor format contains

24 32-bit words and the receive (Rx) descriptor

13 32-bit words (see Table 3-1).

The first two words of the descriptor point to

the next descriptor in the linked list and to the

data buffer associated with the descriptor.

Other words carry additional control

information that affects how the MAC

processes the frame and its data.

A descriptor is required to be aligned on a

32-bit boundary in host memory, although best

performance is achieved if the descriptor is

aligned on a cache-line boundary. The MAC

uses the final two words to report status

information back to the host. See:

Table Description

Table 3-2

Tx control descriptor format

(words 2–13)

Table 3-3

Tx status descriptors

(words 14–23)

Table 3-4

Rx control descriptor

(words 2–3)

Table 3-5

Rx status descriptor

(words 4–12)

Table 3-1. DMA Descriptor Format

Word Bits Field Name Description

0 31:0 link_ptr Link pointer. Contains the address of the next descriptor to be used; must

be 32-bit aligned (bits [1:0] must be 0)

1 31:0 buf_ptr Data buffer pointer. Contains the starting address of the data buffer

associated with this descriptor. A Tx data buffer can begin at any byte

address. A Rx data buffer must be aligned on a 32-bit boundary in host

memory, although best performance is achieved if the Rx data buffer is

cache-line aligned.

(Cache-line size varies from system to system.)

2–13 (Tx)

2–3 (Rx)

31:0 Host-to-

DMA engine

control

information

Additional control information is passed from host to DMA engine. The

format of these words varies depending on whether the descriptor is being

used to Tx a frame from host to PCU, or Rx a frame from PCU to host.

(See

Table 3-2 on page 13, and Table 3-4 on page 24 for details.)

14–23 (Tx)

4–12 (Rx)

31:0 DMA

completion

status

information

Status information reported by the DMA engine when it has finished

processing a descriptor. As with the control information, the format of the

status information differs between Tx and Rx descriptors.

(See

Table 3-3 on page 20, and Table 3-5 on page 24 for details.)

Atheros Communications, Inc. AR9287 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs • 13

COMPANY CONFIDENTIAL February 2010 • 13

The Tx descriptor format for words 2 through

13 is described in Table 3-2.

Table 3-2. Tx Control Descriptor Format (Words 2–13)

Word Bits Field Name Description

2 11:0 frame_length Frame length

Specifies the length, in bytes, of the entire MAC frame, including the frame

check sequence (FCS), initialization vector (IV), and integrity check value

(ICV) fields.

12 vmf Virtual more fragment

If this bit is set, bursting is enabled for this frame. If no burst is in progress, it

initiates a CTS-protected burst if cts_enable is set. If a previous burst is in

progress, it ignores the cts_enable bit and assumes the burst is protected.

13 RES Reserved

14 low_rx_chain When set to 1, indicates that the Rx chain mask switches to low power mode

after transmitting this frame.

15 clear_retry Setting this bit disables the retry bit from being set in the Tx header on a

frame retry (applies to both aggregate and non-aggregate frames).

21:16 tpc_0 Tx power control for series 0

These bits pass unchanged to the baseband, where they are used to control

the transmit power for the frame.

22 rts_enable

Request to send (RTS) enable. At most, one of the

“rts_enable” and

“cts_enable” bits may be set; it is illegal to set both.

set PCU transmits the frame using the RTS/CTS protocol

clear PCU transmits the frame using the contention/backoff protocol

23 veol Virtual end-of-list flag

When set, indicates that the QCU should act as though the descriptor had a

NULL LinkPtr, even if the LinkPtr is not NULL. Must be valid in the final

descriptor of a frame and must be clear for all other descriptors of the frame.

24 clear_dest_mask Clear destination mask bit flag

If set, instructs the PCU and DCU to clear the destination mask bit at the

index specified by the DestIdx field.

28:25 RES Reserved

29 int_req Interrupt request flag

Set to one by the driver to request that the DMA engine generate an interrupt

upon completion of the frame to which this descriptor belongs.

Note that this field must be valid and identical for all descriptors of the

frame; that is, all descriptors for the frame must have this flag set, or all

descriptors for the frame must have this flag clear.

30 dest_index_valid Destination index valid flag

Specifies whether the contents of the DestIdx field are valid.

31 cts_enable Proceed frame with CTS flag

If set, the PCU first sends a CTS before sending the frame described by the

descriptor. Used for 802.11g and Atheros XR frames to quiet legacy stations

before sending a frame the legacy stations cannot interpret (even at the PHY

level). At most, one of the

“rts_enable” and “cts_enable” bits may be set; it

is illegal to set both bits.

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