STM32F411xx：高效Cortex-M4微控制器详解

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STM32F411xx是一款基于ARM Cortex-M4架构的高性能32位微控制器，它集成了浮点单元(FPU)、动态效率线性模式(Batch Acquisition Mode，简称BAM)以及先进的ART Accelerator技术。这款MCU提供了高达100MHz的时钟频率，支持0-wait-state执行，确保了高速运算性能，拥有125 DMIPS的处理能力，这在Dhrystone 2.1基准测试下表现突出，同时也支持密集型数字信号处理(DSP)指令。内存配置上，STM32F411xx配备了512KB的闪存存储器和128KB的SRAM，足以满足大多数应用的需求。对于电源管理，该设备支持宽范围的供电，从1.7V到3.6V，包括电源-on-reset (POR), power-down reset (PDR), voltage detector (PVD) 和 brown-out reset (BOR)。内部集成有4-26MHz的晶体振荡器，以及16MHz工厂预校准的RC振荡器，同时还有一个32kHz用于RTC的高精度振荡器，还提供了一个可校准的内部低频振荡器，以实现精确的时间保持。在功耗方面，运行状态下，当外围设备关闭时，功耗仅为100μA/MHz。如果采用快唤醒的停止模式(Flash in Stop mode)，典型情况下在25°C下为42μA，最大值可达65μA。而在深度休眠模式(Flash in Deep Power Down mode)下，即使在快速唤醒时间内，最低功耗可以达到10μA，最大值为30μA，这使得该芯片非常适合于对能源效率要求极高的应用场合。此外，STM32F411xx还配备了丰富的外设接口，包括11个定时器、1个ADC（模数转换器）和13个通信接口，如USB OTG FS，使其能够广泛应用于工业控制、物联网(IoT)、嵌入式系统设计等领域，对实时性和连接性都有很好的支持。STM32F411xx凭借其强大的处理能力、高效的能效比和广泛的接口选项，是追求高性能和低功耗设计的理想选择。

Functional overview STM32F411xC STM32F411xE

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3 Functional overview

3.1 ARM

Cortex

-M4 with FPU core with embedded Flash and

SRAM

The ARM

Cortex

-M4 with FPU processor is the latest generation of ARM processors for

embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while

delivering outstanding computational performance and an advanced response to interrupts.

The ARM

Cortex

-M4 with FPU 32-bit RISC processor features exceptional code-

efficiency, delivering the high-performance expected from an ARM core in the memory size

usually associated with 8- and 16-bit devices. The processor supports a set of DSP

instructions which allow efficient signal processing and complex algorithm execution. Its

single precision FPU (floating point unit) speeds up software development by using

metalanguage development tools, while avoiding saturation.

The STM32F411xC/xE devices are compatible with all ARM tools and software.

Figure 3 shows the general block diagram of the STM32F411xC/xE.

Note: Cortex

-M4 with FPU is binary compatible with Cortex

-M3.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-

standard ARM

Cortex

-M4 with FPU processors. It balances the inherent performance

advantage of the ARM

Cortex

-M4 with FPU over Flash memory technologies, which

normally requires the processor to wait for the Flash memory at higher frequencies.

To release the processor full 105 DMIPS performance at this frequency, the accelerator

implements an instruction prefetch queue and branch cache, which increases program

execution speed from the -bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 100 MHz.

3.3 Batch Acquisition mode (BAM)

The Batch acquisition mode allows enhanced power efficiency during data batching. It

enables data acquisition through any communication peripherals directly to memory using

the DMA in reduced power consumption as well as data processing while the rest of the

system is in low-power mode (including the flash and ART). For example in an audio

system, a smart combination of PDM audio sample acquisition and processing from the I2S

directly to RAM (flash and ART

™ stopped) with the DMA using BAM followed by some very

short processing from flash allows to drastically reduce the power consumption of the

application. A dedicated application note (AN4515) describes how to implement the

STM32F411xC/xE BAM to allow the best power efficiency.

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STM32F411xC STM32F411xE Functional overview

3.4 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to 8 protected areas that can in turn be divided

up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4

gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.5 Embedded Flash memory

The devices embed up to 512 Kbytes of Flash memory available for storing programs and

data.

To optimize the power consumption the Flash memory can also be switched off in Run or in

Sleep mode (see Section 3.18: Low-power modes). Two modes are available: Flash in Stop

mode or in DeepSleep mode (trade off between power saving and startup time, see

Table 34: Low-power mode wakeup timings(1)). Before disabling the Flash, the code must

be executed from the internal RAM.

3.6 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a software

signature during runtime, to be compared with a reference signature generated at link-time

and stored at a given memory location.

3.7 Embedded SRAM

All devices embed:

• 128 Kbytes of system SRAM which can be accessed (read/write) at CPU clock speed

with 0 wait states

3.8 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves

(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient

operation even when several high-speed peripherals work simultaneously.

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STM32F411xC STM32F411xE Functional overview

3.10 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the

Cortex

-M4 with FPU.

• Closely coupled NVIC gives low-latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving, higher-priority interrupts

• Support tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt

latency.

3.11 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 21 edge-detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 81 GPIOs can be connected

to the 16 external interrupt lines.

3.12 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The

application can then select as system clock either the RC oscillator or an external 4-26 MHz

clock source. This clock can be monitored for failure. If a failure is detected, the system

automatically switches back to the internal RC oscillator and a software interrupt is

generated (if enabled). This clock source is input to a PLL thus allowing to increase the

frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is

available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB

buses is 100 MHz while the maximum frequency of the high-speed APB domains is

100 MHz. The maximum allowed frequency of the low-speed APB domain is 50 MHz.

The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class

performance. In this case, the I

S master clock can generate all standard sampling

frequencies from 8 kHz to 192 kHz.

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