LPC1768嵌入式微控制器：ARM Cortex-M3的强大特性与低功耗设计

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LPC1768/66/65/64是一款基于ARM Cortex-M3架构的嵌入式微控制器，专为低功耗和高度集成的应用设计。这些微控制器的特点在于它们采用了先进的Cortex-M3核心，该核心提供了增强的调试功能和更高级别的系统增强特性。 Cortex-M3处理器具有3级流水线设计，采用哈佛架构，这意味着它拥有独立的本地指令总线和数据总线，以及一个用于外设通信的第三总线。这种设计有助于提高处理速度和效率。内置的预取单元支持推测分支，进一步优化了指令执行流程，提高了程序执行的性能。在硬件资源方面，LPC1768/66/65/64提供了高达512KB的闪存存储，用于存储程序代码，以及多达64KB的数据内存，满足各种数据处理需求。它还包括一个以太网MAC（媒体访问控制）接口，支持网络通信；USB（通用串行总线）设备/主机/全功能OTG（On-The-Go）接口，方便与外部设备的连接和数据交换；一个8通道通用DMA控制器，负责高效地传输数据。此外，该微控制器配备了4个UART（通用异步接收/发送器），用于串行通信；2个CAN（控制器局域网络）通道，适用于工业通信协议；两个SPI（同步串行接口）控制器和3个I2C（Inter-Integrated Circuit）接口，支持多总线通信；一个2输入2输出的I2S（立体声接口）音频接口，便于音频处理；8通道12位ADC（模拟到数字转换器）和10位DAC（数字到模拟转换器），提供高精度的模拟信号转换；电机控制PWM，用于精确的定时和脉宽调制；一个四相编码器接口，以及4个通用定时器和6个输出通用PWM，支持各种定时和脉冲宽度调制应用。为了实现超低功耗，LPC1768/66/65/64还具备节能模式和多种电源管理选项，使得在不同工作负载下能够灵活调整电源消耗，延长电池寿命或在苛刻的能源约束环境中保持高效运行。LPC1768/66/65/64以其高性能、多功能和低功耗特性，是构建高效能嵌入式系统的理想选择。

Objective data sheet Rev. 02 — 11 February 2009 12 of 72

NXP Semiconductors

LPC1768/66/65/64

32-bit ARM Cortex-M3 microcontroller

P2[5]/PWM1[6]/

DTR1/

TRACEDATA[0]

[1]

I/O P2[5] — General purpose digital input/output pin.

O PWM1[6] — Pulse Width Modulator 1, channel 6 output.

O DTR1 — Data Terminal Ready output for UART1.

O TRACEDATA[0] — Trace data, bit 0.

P2[6]/PCAP1[0]/

RI1/TRACECLK

[1]

I/O P2[6] — General purpose digital input/output pin.

I PCAP1[0] — Capture input for PWM1, channel 0.

I RI1 — Ring Indicator input for UART1.

O TRACECLK — Trace Clock.

P2[7]/RD2/

RTS1

[1]

I/O P2[7] — General purpose digital input/output pin.

I RD2 — CAN2 receiver input.

O RTS1 — Request to Send output for UART1.

P2[8]/TD2/

TXD2

[1]

I/O P2[8] — General purpose digital input/output pin.

O TD2 — CAN2 transmitter output.

O TXD2 — Transmitter output for UART2.

P2[9]/

USB_CONNECT/

RXD2

[1]

I/O P2[9] — General purpose digital input/output pin.

O USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor under

software control. Used with the SoftConnect USB feature.

I RXD2 — Receiver input for UART2.

P2[10]/

EINT0/NMI 53

[6]

I/O P2[10] — General purpose digital input/output pin.

Note: LOW on this pin while

RESET is LOW forces on-chip bootloader to take

over control of the part after a reset.

EINT0 — External interrupt 0 input.

I NMI — Non-maskable interrupt input.

P2[11]/

EINT1/

I2STX_CLK

[6]

I/O P2[11] — General purpose digital input/output pin.

EINT1 — External interrupt 1 input.

I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the

slave. Corresponds to the signal SCK in the

S-bus speciﬁcation

(LPC1768/66/65 only).

P2[12]/

EINT2/

I2STX_WS

[6]

I/O P2[12] — General purpose digital input/output pin.

EINT2 — External interrupt 2 input.

I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the

slave. Corresponds to the signal WS in the

S-bus speciﬁcation

. (LPC1768/66/65

only).

P2[13]/

EINT3/

I2STX_SDA

[6]

I/O P2[13] — General purpose digital input/output pin.

EINT3 — External interrupt 3 input.

I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the

S-bus speciﬁcation

(LPC1768/66/65 only).

P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The

operation of port 3 pins depends upon the pin function selected via the pin connect

block. Pins 0 through 24, and 27 through 31 of this port are not available.

P3[25]/MAT0[0]/

PWM1[2]

[1]

I/O P3[25] — General purpose digital input/output pin.

O MAT0[0] — Match output for Timer 0, channel 0.

O PWM1[2] — Pulse Width Modulator 1, output 2.

Table 3. Pin description

…continued

Symbol Pin Type Description

元器件交易网www.cecb2b.com

Objective data sheet Rev. 02 — 11 February 2009 13 of 72

NXP Semiconductors

LPC1768/66/65/64

32-bit ARM Cortex-M3 microcontroller

P3[26]/STCLK/

MAT0[1]/PWM1[3]

[1]

I/O P3[26] — General purpose digital input/output pin.

I STCLK — System tick timer clock input.

O MAT0[1] — Match output for Timer 0, channel 1.

O PWM1[3] — Pulse Width Modulator 1, output 3.

P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The

operation of port 4 pins depends upon the pin function selected via the pin connect

block. Pins 0 through 27, 30, and 31 of this port are not available.

P4[28]/RX_MCLK/

MAT2[0]/TXD3

[1]

I/O P4[28] — General purpose digital input/output pin.

I RX_MCLK — I

S receive master clock. (LPC1768/66/65 only).

O MAT2[0] — Match output for Timer 2, channel 0.

O TXD3 — Transmitter output for UART3.

P4[29]/TX_MCLK/

MAT2[1]/RXD3

[1]

I/O P4[29] — General purpose digital input/output pin.

I TX_MCLK — I

S transmit master clock. (LPC1768/66/65 only).

O MAT2[1] — Match output for Timer 2, channel 1.

I RXD3 — Receiver input for UART3.

TDO/SWO 1

[1]

O TDO — Test Data out for JTAG interface.

O SWO — Serial wire trace output.

TDI 2

[1]

I TDI — Test Data in for JTAG interface.

TMS/SWDIO 3

[1]

I TMS — Test Mode Select for JTAG interface.

I/O SWDIO — Serial wire debug data input/output.

TRST 4

[1]

I TRST — Test Reset for JTAG interface.

TCK/SWDCLK 5

[1]

I TCK — Test Clock for JTAG interface.

I SWDCLK — Serial wire clock.

RTCK 100

[1]

I/O RTCK — JTAG interface control signal.

RSTOUT 14 O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC1768/66/65/64

being in Reset state.

RESET 17

[7]

I External reset input: A LOW on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to begin at

address 0. TTL with hysteresis, 5 V tolerant.

XTAL1 22

[8]

I Input to the oscillator circuit and internal clock generator circuits.

XTAL2 23

[8]

O Output from the oscillator ampliﬁer.

RTCX1 16

[8]

I Input to the RTC oscillator circuit.

RTCX2 18

[8]

O Output from the RTC oscillator circuit.

31, 41,

55, 72,

97, 83

[8]

I ground: 0 V reference.

SSA

[8]

I analog ground: 0 V reference. This should nominally be the same voltage as V

but should be isolated to minimize noise and error.

DD(3V3)

28, 54,

71, 96

[8]

I 3.3 V supply voltage: This is the power supply voltage for the I/O ports.

DD(REG)(3V3)

42, 84

[8]

I 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip

voltage regulator only.

Table 3. Pin description

…continued

Symbol Pin Type Description

元器件交易网www.cecb2b.com

Objective data sheet Rev. 02 — 11 February 2009 14 of 72

NXP Semiconductors

LPC1768/66/65/64

32-bit ARM Cortex-M3 microcontroller

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When conﬁgured as a ADC input,

digital section of the pad is disabled.

[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When conﬁgured as the DAC output,

digital section of the pad is disabled.

[4] Open-drain 5 V tolerant digital I/O pad, compatible with I

C-bus 400 kHz speciﬁcation. This pad requires an external pull-up to provide

output functionality. When power is switched off, this pin connected to the I

C-bus is ﬂoating and does not disturb the I

C lines.

Open-drain conﬁguration applies to all functions on this pin.

[5] Pad provides digital I/O and USB functions. It is designed in accordance with the

USB speciﬁcation, revision 2.0

(Full-speed and

Low-speed mode only).

[6] 5 V tolerant pad with 5 ns glitch ﬁlter providing digital I/O functions with TTL levels and hysteresis.

[7] 5 V tolerant pad with 20 ns glitch ﬁlter providing digital I/O function with TTL levels and hysteresis.

[8] Pad provides special analog functionality.

7. Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the

system bus and are used similarly to TCM interfaces: one bus dedicated for instruction

fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for

simultaneous operations if concurrent operations target different devices.

The LPC1768/66/65/64 use a multi-layer AHB matrix to connect the ARM Cortex-M3

buses and other bus masters to peripherals in a ﬂexible manner that optimizes

performance by allowing peripherals that are on different slaves ports of the matrix to be

accessed simultaneously by different bus masters.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,

interruptable/continuable multiple load and store instructions, automatic state save and

restore for interrupts, tightly integrated interrupt controller with wakeup interrupt controller,

and multiple core buses capable of simultaneous accesses.

DDA

[8]

I analog 3.3 V pad supply voltage: This should be nominally the same voltage as

DD(3V3)

but should be isolated to minimize noise and error. This voltage is used to

power the ADC and DAC.

VREFP 12

[8]

I ADC positive reference voltage: This should be nominally the same voltage as

DDA

but should be isolated to minimize noise and error. Level on this pin is used

as a reference for ADC and DAC.

VREFN 15 I ADC negative reference voltage: This should be nominally the same voltage as

but should be isolated to minimize noise and error. Level on this pin is used as

a reference for ADC and DAC.

VBAT 19

[8]

I RTC pin power supply: 3.3 V on this pin supplies the power to the RTC

peripheral.

n.c. 13 - not connected

Table 3. Pin description

…continued

Symbol Pin Type Description

元器件交易网www.cecb2b.com

Objective data sheet Rev. 02 — 11 February 2009 15 of 72

NXP Semiconductors

LPC1768/66/65/64

32-bit ARM Cortex-M3 microcontroller

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual that can be found on ofﬁcial ARM website.

7.3 On-chip ﬂash program memory

The LPC1768/66/65/64 contain up to 512 kB of on-chip ﬂash memory. A new two-port

ﬂash accelerator maximizes performance for use with the two fast AHB-Lite buses.

7.4 On-chip SRAM

The LPC1768/66/65/64 contain a total of 64 kB on-chip static RAM memory. This includes

the main 32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus,

and two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB

multilayer matrix.

This architecture allows CPU and DMA accesses to be spread over three separate RAMs

that can be accessed simultaneously.

7.5 Memory Protection Unit (MPU)

The LPC1768/66/65/64 have a Memory Protection Unit (MPU) which can be used to

improve the reliability of an embedded system by protecting critical data within the user

application.

The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory regions, allowing memory regions to be deﬁned as read-only

and detecting unexpected memory accesses that could potentially break the system.

The MPU separates the memory into distinct regions and implements protection by

preventing disallowed accesses. The MPU supports up to 8 regions each of which can be

divided into 8 subregions. Accesses to memory locations that are not deﬁned in the MPU

regions, or not permitted by the region setting, will cause the Memory Management Fault

exception to take place.

7.6 Memory map

The LPC17xx incorporates several distinct memory regions, shown in the following

ﬁgures. Figure 3 shows the overall map of the entire address space from the user program

viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.

The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.

Each peripheral of either type is allocated 16 kB of space. This allows simplifying the

address decoding for each peripheral.

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