基于遗传算法的CPU压力测试框架GeST：自动化设计与应用

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"GeST: An Automatic Framework for Generating CPU Stress-Tests 是一篇由 Shidhartha Das 发表在 IEEE 上的论文，该研究专注于开发一个基于遗传算法的自动CPU压力测试框架。这个创新的工具旨在自动化压力测试过程，特别针对X86和ARM架构的处理器，能够优化包括但不限于功率（power）、每周期执行的指令数（Instructions Per Cycle, IPC）、温度以及电压变化率（dI/dt voltage noise）等关键性能指标。论文的核心概念是将遗传算法应用到CPU压力测试的设计中，通过模拟自然选择和遗传机制来搜索最能挑战CPU极限的工作负载。与传统的基准测试和手工编写的压力测试相比，GeST能够更深入地挖掘和评估硬件的性能边界。其设计的灵活性体现在用户可以根据需要自定义测量函数和适应度函数，选择要参与搜索的特定CPU指令集。为了展示框架的广泛适用性和有效性，研究者展示了在不同类型的平台上的应用，涵盖了低功耗移动ARM处理器到高性能x86处理器。此外，框架还支持使用各种测量工具，如示波器，这增加了测试的精确性和多样性。值得注意的是，论文提供的代码是开源的，这使得其他研究人员和开发者能够轻松获取并进一步改进这个工具，使其适应他们特定的硬件环境和测试需求。GeST不仅提升了CPU压力测试的效率，还因其可扩展性和灵活性而成为评估和优化现代CPU性能的强大工具。"

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Shidhartha Das

Arm

Shidhartha.Das@arm.com

GeST: An Automatic Framework For Generating

CPU Stress-Tests

Abstract—This work presents GeST (Generator for Stress-Tests): a

framework for

automatically generating

CPU stress-tests. The

framework is based on genetic algorithm search and can be used to

maximize different target CPU metrics such as power, temperature,

instructions executed per cycle and dI/dt voltage noise. We

demonstrate the generality and effectiveness of the framework by

generating various workloads that stress the CPU power, thermal

and voltage margins more than both

conventional benchmarks

and

manually written stress-tests. The key framework strengths are its

extensibility and flexibility. The user can specify custom

measurement and fitness functions as well as the CPU instructions

that will be used in the genetic algorithm search. The paper

demonstrates the framework prowess by using it with simple and

complex fitness functions to generate stress-tests: a) for various

platform

types ranging from low-power mobile ARM CPUs to high-

power x86 CPUs and b) with different measurement instruments

such as oscilloscopes and software accessible performance counters

and sensors.

Keywords: tool, framework, stress-test, virus, power, temperature,

dI/dt, genetic algorithms

I. INTRODUCTION

Stress

tests that maximize micro-architectural activity, heat-

dissipation, power-consumption and voltage-noise are useful for

numerous reasons that include among other: a) benchmarking,

b) testing system stability, c) margining production systems, d)

detecting performance bottlenecks or weaknesses in the CPU

power delivery network (PDN), and e) testing the efficacy of

energy-efficiency techniques such as voltage-noise mitigation

mechanisms [1][2][3][4][5][6][13]. Manually crafting such

stress-tests is a time consuming and tedious procedure.

Consequently, previous work has proposed automated

frameworks for generating stress-

tests

[1][2][3][4][5][6][7][8].

The basis of most of these approaches is genetic algorithm

search (GA) [9].

Despite the previous work on GA based stress-test

generation frameworks, to the best of our knowledge, there is no

publicly available tool for researchers and practitioners for

automatic stress-test generation. This work presents GeST

(Generator for Stress-Tests): a GA based framework that

researchers and designers can use for automatic stress-test

generation. GeST has already been used for industrial purposes

and in several research publications [22][23][24][25].

GeST, given a user-specified set of assembly instructions

and operands, attempts to find the instruction mix, order and

operands that maximize a target metric. GeST is extensible as it

offers an easy interface to build upon. A user

can

define the

instructions, which the optimization search uses, by only

changing input configuration parameters. This renders the

framework compatible with any ISA. Moreover, an

experimenter can script custom measurement procedures and

custom fitness functions (the function that drives the GA

optimiz

ation)

in a plug-and-play fashion using the template

measurement and fitness software classes provided in the

framework. The user defined measurement scripts and fitness

functions are easy to integrate in the framework by simply

changing the configuration parameters without performing any

change in the framework’s core source code. We demonstrate

the power of the framework’s extensibility and flexibility by: a)

generating stress-tests that maximize different target metrics

such as power, temperature, and dI/dt voltage-noise, b) using the

framework with various measurement procedures and

optimization metrics such as software accessible counters (e.g.

performance counters) and external instruments (such as

oscilloscopes), c) generating stress-tests on mobile ARM and

server-grade ARM and x86 CPUs, d) generating stress-tests on

bare-metal and OS execution environments, and e) using both

simple as well as complex multi-objective fitness functions.

The rest of the paper is organized as follows: Section II

provides background discussion on stress-tests

, Section

III

presents GeST, Section IV discusses the experimental setup,

Section V demonstrates the capability of GeST to generate

stress-tests that maximize power consumption, temperature and

IPC. In Section VI, we highlight the framework’s capability to

generate dI/dt voltage noise stress-tests.

Section

VII discusses

previously proposed GA frameworks. Finally, we present

concluding remarks in Section VIII.

II. B

ACKGROUND ON STRESS-TESTS

For the purposes of this discussion, we classify stress-tests

into three categories: a) stress-

tests that maximize specific

micro-architectural (uArch) metrics, such as memory

bandwidth, IPC and cache-misses, b) stress-tests that maximize

power consumption and temperature, commonly referred to as

“power-viruses”, and c) stress-tests that maximize voltage noise,

also known as “voltage-

noise viruses” or

“dI/dt-viruses”. This

work shows that GeST can successfully generate stress-tests for

all three categories. In particular, we use the framework to

generate stress-tests that maximize CPU IPC, power,

temperature and dI/dt voltage-noise. While this work focuses on

the CPU there is nothing fundamental that prevents using GeST

for other

processor

components as well, for instance the last

level cache (LLC) or an integrated accelerator. A brief

discussion on each of the three stress-tests categories follows.

Zacharias Hadjilambrou

University of Cyprus

zhadji01@cs.ucy.ac.cy

Paul N Whatmough

Arm / Harvard University

Paul.whatmough@arm.com

David Bull

Arm

dbull@arm.com

Yiannakis Sazeides

University of Cyprus

yanos@cs.ucy.ac.cy

2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

DOI 10.1109/ISPASS.2019.00009

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