ETSI TS 102 694-1: SmartCard Terminal测试规范详解

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ETSI TS 102 694-1 V10.2.0 (2015-03) 是一份关于智能卡（SmartCard）单线协议（Single Wire Protocol, SWP）接口的测试规范，主要涵盖了SWP终端的测试步骤和特性。该技术规范是Release 10版本，由欧洲电信标准协会（European Telecommunications Standards Institute, ETSI）发布。这篇文档旨在为研发和测试人员提供详细指导，以确保SWP终端的功能正确性和兼容性。SWP是一种通信协议，用于在智能卡和读卡器之间通过单一导线进行数据交换，常应用于移动支付、身份验证等场景。测试规范的目的是确保终端设备遵循SWP标准，提高系统的稳定性和安全性。测试规范中可能包括以下几个方面： 1. **接口定义**：详细描述SWP接口的物理层和数据链路层特性，包括信号电平、时序、帧结构以及错误检测机制。 2. **功能测试**：涵盖SWP终端的基本功能，如命令传输、响应接收、错误处理和重试机制等，确保终端能够正确地执行各种操作。 3. **性能测试**：评估SWP终端在不同条件下的传输速率、功耗、抗干扰能力等性能指标，以满足实际应用的需求。 4. **兼容性测试**：确保SWP终端与其他符合标准的智能卡和读卡器设备之间的互操作性。 5. **安全测试**：针对SWP协议的安全特性进行测试，如加密、完整性保护和防止欺诈攻击等，确保交易过程的安全。 6. **故障恢复测试**：检查终端在遇到通信故障或硬件问题时的恢复能力，以确保系统可靠性。 7. **测试方法和流程**：提供详细的测试用例、步骤和预期结果，帮助测试工程师按照标准流程进行系统验证。 8. **参考标准和规范**：列出相关的国际和行业标准，如ISO/IEC 7816系列，作为SWP测试的依据。 9. **文档和报告**：规定了测试报告应包含的内容和格式，以便于问题分析和改进。通过遵循这份测试规范，开发人员和测试团队可以确保他们的SWP终端产品符合行业标准，减少因兼容性问题导致的问题，并提高用户体验。同时，这也对提升整个行业的质量和一致性起到了关键作用。

ETSI

ETSI TS 102 694

1 V10.2.0 (2015

03)

Release 10

4.2 Applicability table

Table 4.2 a) specifies the applicability of each test case to the device under test. See clause 3.4 for the format of table 4.2 a).

Table 4.2 a): Applicability of tests

Test ca

Description

Release

Execution

requirements

Rel

Terminal

Rel

Terminal

Rel

Terminal

Rel

Terminal

Support

System architecture tests

(Test cases for this clause are FFS)

Physical characteristics tests

5.3.2.2.2 Activation of SWP additionally to other interface Rel-7 C001 C001 C001 C001

5.3.2.2.3 Activation of SWP in low power mode Rel-7 C002 C002 C002 C002

5.3.2.3.2 SWP initial activation in full power mode - normal procedure Rel-7 C001 C001 C001 C001

5.3.2.3.4 SWP initial activation in full power mode - corrupted ACT_SYNC frame (repeat the last

frame)

Rel-7 C001 C001 C001 C001

5.3.2.3.5 SWP initial activation in full power mode - no ACT_SYNC frame (repeat the last frame) Rel-7 C001 C001 C001 C001

5.3.2.3.6 SWP initial activation failed in full power mode - corrupted ACT_SYNC frame (multiple) Rel-7 C001 C001 C001 C001

5.3.2.3.7 SWP initial activation failed in full power mode - no ACT_SYNC frame (multiple) Rel-7 C001 C001 C001 C001

5.3.2.3.8 SWP Initial activation in full power mode - corrupted ACT_READY frame (repeat last

frame)

Rel-7 C001 C001 C001 C001

5.3.2.3.9 Void

5.3.2.3.9a SWP Initial activation in full power mode - no ACT_READY frame (repeat last frame) Rel-10 N/A N/A N/A C001

5.3.2.3.10 SWP initial activation failed in full power mode - corrupted ACT_READY frame

(multiple)

Rel-7 C001 C001 C001 C001

5.3.2.3.11 SWP initial activation failed in full power mode - no ACT_READY frame (multiple) Rel-7 C001 C001 C001 C001

5.3.2.3.12 SWP initial activation in low power mode Rel-7 C002 C002 C002 C002

5.3.2.3.13 SWP initial activation in low power mode - corrupted ACT_SYNC frame (repeat the

last frame)

Rel-7 C002 C002 C002 C002

5.3.2.3.14 SWP initial activation in low power mode - no ACT_SYNC frame (repeat the last

frame)

Rel-7 C002 C002 C002 C002

5.3.2.3.15 SWP initial activation failed in low power mode - corrupted ACT_SYNC frame

(multiple)

Rel-7 C002 C002 C002 C002

5.3.2.3.16 SWP initial activation failed in low power mode - no ACT_SYNC frame (multiple) Rel-7 C002 C002 C002 C002

5.3.2.3.17 SWP subsequent activation in full power mode Rel-7 C115 C115 C001 C001

5.3.2.3.19 SWP initial activation in full power mode - send ACT frames in wrong order,

ACT_READY frame after activation (repeat the last frame)

Rel-7 C001 C001 C001 C001

Electrical characteristics tests

5.4.1.3.2 Current provided in low power mode, no spikes Rel-7 C002 C002 C002 C002

5.4.1.3.3 Current provided in low power mode, with spikes Rel-7 C002 C002 C002 C002

5.4.1.4.2 Communication with S2 variation in full power mode Rel-7 C001 C001 C001 C001

5.4.1.4.3 Communication with S2 variation in low power mode Rel-7 C002 C002 C002 C002

5.4.1.5.2.2 Communication with S2 variation in full power mode Rel-7 C001 C001 C001 C001

5.4.1.5.2.3 Communication with S2 variation in low power mode Rel-7 C002 C002 C002 C002

Physical transmission layer tests

ETSI

ETSI TS 102 694

1 V10.2.0 (2015

03)

Release 10

Test ca

Description

Release

Execution

requirements

Rel

Terminal

Rel

Terminal

Rel

Terminal

Rel

Terminal

Support

5.5.1.2 S1 waveforms, default bit duration Rel-7 M M M M

5.5.1.3 S1 waveforms, extended bit durations Rel-7 C013 C013 C013 C013

5.5.3.2 SWP states and transitions, communication Rel-7 M M

5.5.3.3 SWP resume after upper layer indication that the UICC requires no more activity on

this interface

Rel-7 TR2 N/A N/A C116 C116

5.5.4.2 Power provided in full power mode, SWP Rel-7 C001 C001 C001 C001

5.5.4.3 Switching from full to low power mode Rel-7 C110 C110 C110 C110

5.5.4.4 Switching from low to full power mode Rel-7 C111 C111 C111 C111

Data link layer tests

5.6.2.2.2 Interpretation of incorrectly formed frames - SHDLC RSET frames Rel-7 M M M M

5.6.2.2.3 Interpretation of incorrectly formed frames - SHDLC I-frames Rel-7 M M M M

5.6.2.3.2 Behavior of CLF with bit stuffing in frame Rel-7 M M M M

5.6.3.2.2 Ignore ACT LLC frame reception after the SHDLC link establishment Rel-7 M M M M

5.6.3.2.3 Ignore ACT LLC frame reception in CLT session Rel-7 TR3 C008 C008 C008 C008

5.6.3.2.5 Closing condition of CLT session whereas SHDLC link has been established before

CLT session

Rel-7 TR3 C011 C011 C011 C011

5.6.4.2.2 Not matching SYNC_ID verification in low power mode Rel-7 TR3 C117 C117 C117 C117

SHDLC LLC definition tests

5.7.1.2 Data passed up to the next layer Rel-7 C009 C009 C009 C009

5.7.1.3 Error management - corrupted I-frame Rel-7 M M M M

5.7.1.4 Error management - corrupted RR frame Rel-7 TR1 M M M M

5.7.6.4.2 Initial state at link reset - reset by the UICC Rel-7 TR1 M M M M

5.7.7.3.2 Link establishment by the UICC Rel-7 M M M M

5.7.7.3.3 Link establishment and connection time out Rel-7 M M M M

5.7.7.3.4 Requesting unsupported window size and/or SREJ support - link establishment by

UICC

Rel-7 C107 C107 C107 C107

5.7.7.3.5 Forcing lower window size and SREJ not used - link establishment by the T Rel-7 C108 C108 C108 C108

5.7.7.3.6 Discard buffered frames on link re-establishment Rel-7 C102 C102 C102 C102

5.7.7.5.2 I-frame transmission Rel-7 TR2/TR1

(see note)

M M M M

5.7.7.5.3 I-frame reception - single I-Frame reception Rel-7 TR2/TR1 (see

note)

M M M M

5.7.7.5.4 I-frame reception - multiple I-Frame reception Rel-7 TR2/TR1 (see

note)

M M M M

5.7.7.6.2 REJ transmission - multiple I-frames received Rel-7 C101 C101 C101 C101

5.7.7.6.3 REJ reception Rel-7 TR2/TR1

(see note)

C114 C114 C114 C114

5.7.7.7.2 Retransmission of multiple frames Rel-7 TR2/TR1

(see note)

M M M M

5.7.7.8.2 RNR reception Rel-7 TR2/TR1

(see note)

M M M M

5.7.7.8.3 Empty I-frame transmission Rel-7 TR1 M M M M

5.7.7.9.2 SREJ transmission Rel-7 C102 C102 C102 C102

ETSI

ETSI TS 102 694

1 V10.2.0 (2015

03)

Release 10

Test ca

Description

Release

Execution

requirements

Rel

Terminal

Rel

Terminal

Rel

Terminal

Rel

Terminal

Support

5.7.7.9.4 SREJ reception Rel-7 TR2/TR1

(see note)

C102 C102 C102 C102

CLT LLC definition tests

5.8.5.2 ISO/IEC 14443-3 [5] Type A, no administrative command Rel-7 TR1, TR3 C008 C008 C008 C008

5.8.6.3.1.2 Opening a CLT session with CL_PROTO_INF(A) Rel-7 TR1 C008 C008 C008 C008

5.8.6.3.2.2 Opening a CLT session with CL_PROTO_INF(F) Rel-7 TR1 N/A N/A C113 C113

5.8.6.3.2.3 Empty CLT(F) Frame Rel-7 TR1 N/A N/A C113 C113

5.8.6.3.2.4 RF off during CLT session not expecting Empty CLT Rel-7 TR1 N/A N/A C113 C113

5.8.6.3.2.5 RF off during CLT session expecting Empty CLT Rel-7 TR1 N/A N/A C113 C113

Timing and performance tests

5.9.1.2.2 Transceiving non-chained data over RF in Card Emulation Rel-7 TR2 N/A N/A C112 C112

5.9.2.1.2 CLF processing time - Type A aligned communication, with RF response Rel-7 TR1, TR3 C008 C008 C008 C008

5.9.2.1.3 CLF processing time, no RF response Rel-7 TR1, TR3 C008 C008 C008 C008

5.9.2.2.2 CLF processing time, Request Guard Time from IDLE state - Type A state transition Rel-7 TR1, TR3 C008 C008 C008 C008

5.9.2.2.3 CLF processing time, Request Guard Time from HALT state - Type A state transition Rel-7 TR1, TR3 C008 C008 C008 C008

NOTE: The test case shall be executed with TR2 if available, otherwise TR1 shall be used.

Table 4.2 b): Conditional items referenced by table 4.2 a)

Conditional item

Condition

C001 IF (O_CLASS_B OR O_CLASS_C_FULL) THEN M ELSE N/A

C002 IF O_CLASS_C_LOW THEN M ELSE N/A

C003 Void

C004 Void

C005 IF O_102_600 THEN M ELSE N/A

C006 IF O_DEAC_SUBACT_FULL THEN M ELSE N/A (see note)

C007 Void

C008 IF (O_CLT_A FULL OR O_CLT_A_EXTENDED_ONLY) THEN M ELSE N/A

C009 IF O_102_622 THEN M ELSE N/A

C010 Void

C011 IF (O_CLT_A FULL OR O_CLT_A_EXTENDED_ONLY OR CLT_F) THEN M ELSE N/A

C012 Void

C013 IF O_EXTENDED_T THEN M ELSE N/A

C101 IF O_WS_3 THEN M ELSE N/A

C102 IF O_SREJ THEN M ELSE N/A

C103 Void

C104 Void

C105 Void

C106 IF O_SREJ AND O_WS_3 THEN M ELSE N/A

C107 IF NOT (O_SREJ AND O_WS_4) THEN M ELSE N/A

C108 IF O_WS_3 OR O_SREJ THEN M ELSE N/A

C109 Void

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