QSFP+模块技术规范：SFF-8436 Rev4.2详解

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"SFF-8436 V42.PDF是QSFP+模块协议的详细规范，涵盖了电气、光学和机械特性，旨在为系统制造商、系统集成商和驱动供应商提供统一标准。此文档修订至第四版第二版，发布于2012年3月21日，增加了对10Gbps数据速率的支持，并更新了机械规格。" QSFP+模块，全称Quad Small Form-factor Pluggable Plus，是一种高速网络接口标准，用于数据中心、电信网络和存储区域网络等应用场景。SFF-8436规范是定义QSFP+模块及其连接器的关键文件，它定义了模块的寄存器地址，明确了引脚功能，同时详细阐述了软硬件的时序要求。 1. **电气特性**：SFF-8436规定了QSFP+模块在铜缆连接下的电气性能，包括信号完整性、电源需求、接地规则以及信号传输速率。在本版本中，特别强调了支持10Gbps的数据速率，这对于高速数据传输至关重要。 2. **光学特性**：光学特性部分涵盖了光发射机和接收机的性能参数，如光功率、灵敏度、波长、光学接口和光学信号质量。这些参数确保了光信号在光纤上的可靠传输。 3. **机械特性**：机械特性包括QSFP+模块的物理尺寸、插拔接口、连接器的机械设计和热管理。这一部分的更新可能涉及到模块的外形尺寸、插拔力、散热设计等，以适应不断提升的数据速率和更紧凑的设备空间。 4. **寄存器定义**：QSFP+模块内部有多个寄存器，用于配置、监控和诊断模块状态。这些寄存器的地址和功能在SFF-8436中被详细定义，使得系统可以读取或写入这些寄存器来控制模块的工作模式和获取运行状态。 5. **软硬件时序**：协议详细说明了模块与主机系统之间的通信时序，包括初始化序列、数据传输、错误处理和状态报告。这确保了模块和系统间的无缝配合。 6. **公共标准**：SFF-8436是系统制造商、集成商和供应商的通用标准，旨在促进兼容性和互操作性，减少行业内的设计复杂性和成本。 7. **公开审查和评论**：该文档允许公众查看并提交反馈，以促进未来版本的改进和完善。成员公司将考虑读者的评论，将其纳入后续修订。 SFF-8436 V42.PDF是QSFP+模块技术的重要参考，对于理解其工作原理、设计兼容系统或开发相关产品具有深远的影响。

Published SFF-8436 Rev 4.2

QSFP+ 10 Gbs 4X Pluggable Transceiver Page 15

Table 3: Pin Function Definition (See Figure 10 for pad dimensions)

Logic Symbol Description Plug

Sequence

Notes

1 GND Ground 1 1

2 CML-I Tx2n Transmitter Inverted Data Input 3

3 CML-I Tx2p Transmitter Non-Inverted Data Input 3

4 GND Ground 1 1

5 CML-I Tx4n Transmitter Inverted Data Input 3

6 CML-I Tx4p Transmitter Non-Inverted Data Input 3

7 GND Ground 1 1

8 LVTTL-I

ModSelL

Module Select 3

9 LVTTL-I

ResetL Module Reset 3

10 Vcc Rx +3.3V Power Supply Receiver 2 2

11 LVCMOS-

I/O

SCL 2-wire serial interface clock 3

12 LVCMOS-

I/O

SDA 2-wire serial interface data 3

13 GND Ground 1 1

14 CML-O Rx3p Receiver Non-Inverted Data Output 3

15 CML-O Rx3n Receiver Inverted Data Output 3

16 GND Ground 1 1

17 CML-O Rx1p Receiver Non-Inverted Data Output 3

18 CML-O Rx1n Receiver Inverted Data Output 3

19 GND Ground 1 1

20 GND Ground 1 1

21 CML-O Rx2n Receiver Inverted Data Output 3

22 CML-O Rx2p Receiver Non-Inverted Data Output 3

23 GND Ground 1 1

24 CML-O Rx4n Receiver Inverted Data Output 3

25 CML-O Rx4p Receiver Non-Inverted Data Output 3

26 GND Ground 1 1

27 LVTTL-O

ModPrsL

Module Present 3

28 LVTTL-O

IntL Interrupt 3

29 Vcc Tx +3.3V Power supply transmitter 2 2

30 Vcc1 +3.3V Power supply 2 2

31 LVTTL-I

LPMode Low Power Mode 3

32 GND Ground 1 1

33 CML-I Tx3p Transmitter Non-Inverted Data Input 3

34 CML-I Tx3n Transmitter Inverted Data Input 3

35 GND Ground 1 1

36 CML-I Tx1p Transmitter Non-Inverted Data Input 3

37 CML-I Tx1n Transmitter Inverted Data Input 3

38 GND Ground 1 1

Note 1: GND is the symbol for signal and supply (power) common for the QSFP+

module. All are common within the QSFP+ module and all module voltages are

referenced to this potential unless otherwise noted. Connect these directly to the

host board signal-common ground plane.

Note 2: Vcc Rx, V

cc1 and Vcc Tx are the receiver and transmitter power supplies and

shall be applied concurrently. Requirements defined for the host side of the Host

Edge Card Connector are listed in Table 6. Recommended host board power supply

filtering is shown in Figures 3 and 4. Vcc Rx Vcc1 and Vcc Tx may be internally

connected within the QSFP+ Module in any combination. The connector pins are each

rated for a maximum current of 500 mA.

Figure 3 shows an example of a complete QSFP+ host PCB schematic with connections to

SerDes and control ICs.

Published SFF-8436 Rev 4.2

QSFP+ 10 Gbs 4X Pluggable Transceiver Page 18

ModPrsL

IntL

4.1.1.1 ModSelL

The ModSelL is an input pin. When held low by the host, the module responds to 2-wire

serial communication commands. The ModSelL allows the use of multiple QSFP+ modules on a

single 2-wire interface bus. When the ModSelL is “High”, the module shall not respond to

or acknowledge any 2-wire interface communication from the host. ModSelL signal input

node must be biased to the “High” state in the module.

In order to avoid conflicts, the host system shall not attempt 2-wire interface

communications within the ModSelL de-assert time after any QSFP+ modules are deselected.

Similarly, the host must wait at least for the period of the ModSelL assert time before

communicating with the newly selected module. The assertion and de-asserting periods of

different modules may overlap as long as the above timing requirements are met.

4.1.1.2 ResetL

The ResetL pin must be pulled to Vcc in the QSFP+ module. A low level on the ResetL pin

for longer than the minimum pulse length (t_Reset_init) initiates a complete module

reset, returning all user module settings to their default state. Module Reset Assert

Time (t_init) starts on the rising edge after the low level on the ResetL pin is

released. During the execution of a reset (t_init) the host shall disregard all status

bits until the module indicates a completion of the reset interrupt. The module indicates

this by asserting “low” an IntL signal with the Data_Not_Ready bit negated. Note that on

power up (including hot insertion) the module should post this completion of reset

interrupt without requiring a reset.

4.1.1.3 LPMode

The LPMode pin shall be pulled up to Vcc in the QSFP+ module. This function is affected

by the LPMode pin and the combination of the Power_over-ride and Power_set software

control bits (Address A0h, byte 93 bits 0,1).

The module has two modes a low power mode and a high power mode. The high power mode

operates in one of the four power classes.

When the module is in a low power mode it has a maximum power consumption of 1.5W. This

protects hosts that are not capable of cooling higher power modules, should such modules

be accidentally inserted.

The modules 2-wire serial interface and all laser safety functions must be fully

operational in this low power mode. The module shall still support the completion of

reset interrupt in this low power mode.

If the Extended Identifier bits (Page 00h, byte 129 bits 6-7) indicate a power

consumption greater than 1.5W and the module is in low power mode it must reduce its

power consumption to less than 1.5W while still maintaining the functionality above. The

exact method of accomplishing low power is not specified, however it is likely that

either the Tx or Rx or both will not be operational in this state.

If the Extended Identifier bits (Page 00h, byte 129 bits 6-7) indicate that its power

consumption is less than 1.5W then the module shall be fully functional independent of

whether it is in low power or high power mode.

The Module should be in low power mode if the LPMode pin is in the high state, or if the

Power_ override bit is in the high state and the Power_set bit is also high. The

module should be in high power mode if the LPMode pin is in the low state, or the

Power_override bit is high and the Power_set bit is low. Note that the default state

for the Power_override bit is low.

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