"EPCS1/EPCS4串行FLASH配置芯片数据手册.pdf" - CSDN文库

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4 Altera Corporation

Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet

Pin Description

As shown in Figure 1, the serial configuration device is an 8-pin device.

The control pins on the serial configuration device are: serial data output

(DATA), active serial data input ( ASDI ), serial clock ( DCLK), and chip select

(nCS). Table 3 shows the serial configuration device ’ s pin descriptions.

Programming

& Configuration

File Support

The Quartus II design software provides programming support for serial

configuration devices. After selecting the serial configuration device, the

Quartus II software automatically generates the Programmer Object File

(.pof ) to program the device. The software allows users to select the

appropriate serial configuration device density that most efficiently stores

the configuration data for a selected Cyclone FPGA.

Serial configuration devices are programmed using the APU with the

appropriate programming adapter (PLMSEPC-8) via the Quartus II

software or the ByteBlaster II download cable via the Quartus II software.

In addition, many third-party programmers, such as BP Microsystems

and System General, offer programming hardware that supports serial

configuration devices.

Table 3. Serial Configuration Device Pin Description

Pin Name Pin Number Pin Type Description

DATA 2 Output DATA output signal transfers the data serially out of the serial

configuration device into the Cyclone FPGA during

read/configuration operation. During a read/configuration operation,

the serial configuration device is enabled by pulling nCS low. The

DATA signal transitions on the falling edge of DCLK.

ASDI 5 Input Active serial data input signal is used to transfer data serially into the

serial configuration device. It receives the data that should be

programmed into the serial configuration device. Values register on

the rising edge of DCLK.

nCS 1 Input Active low chip select input signal toggles at the beginning and end

of a valid instruction. When this signal is high, the device is

deselected and the DATA signal is tri-stated. When the signal is low,

it enables the device and puts the device in an active mode. After

power up, the serial configuration device requires a falling edge on

the nCS signal before beginning any operation.

DCLK 6 Input DCLK is provided by the Cyclone FPGA. This signal provides the

timing of the serial interface. The data presented at ASDI are latched

in to the serial configuration device, at the rising edge of DCLK . Data

on the DATA pin changes after the falling edge of DCLK and is latched

into the Cyclone FPGA on the rising edge.

VCC 3, 7, 8 Power Power pins connect to 3.3 V.

GND 4 Ground Ground pin.

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