内存技术演进：从DDR到DDR3 SDRAM

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"关于内存Jacob，这是一份深入学习内存技术发展的重要资料，被誉为经典之作，推荐大家仔细研读。内容涵盖了缓存、DRAM和磁盘等存储层次的详细知识。" 本文主要讨论了内存系统中的关键组件，包括缓存（Cache）、动态随机访问存储器（DRAM）以及磁盘存储，这些都是现代计算机系统中不可或缺的部分。首先，我们来看DDR（Double Data Rate）内存技术的发展。 DDR内存技术通过在时钟周期的上升沿和下降沿同时传输数据，显著提高了数据传输速率。DDR2在此基础上进一步优化，提升了内存带宽，降低了功耗。图12.20展示了DDR内存中的列读取和列写入命令的进步，列读取命令的数据与数据 strobe信号边缘对齐，而列写入命令的数据由DRAM控制器发送，与DQ和DQS#数据 strobe信号中心对齐，这种设计优化了数据传输效率。接下来，图12.21比较了TSOP封装的DDRSDRAM设备和Fine Ball Grid Array (FBGA)封装的DDR2SDRAM设备。FBGA封装虽然成本较高，但由于其球栅阵列接触点带来的电气寄生参数更小，因此对于高数据速率的DDR2设备是必需的，而对于DDRSDRAM设备则是可选项。这种封装技术改进了信号传输线的性能，以适应更高的数据速率要求。随着DDR和DDR2的成功，内存制造商继续沿着提高DRAM设备预取长度的道路前进，以支持新一代商品级DRAM设备的更高数据速率。DDR3SDRAM是这一进化过程中的一个重要里程碑，它在DDR2的基础上再次提升了预取长度，从而实现了更高的设备数据速率，并引入了更多的节能技术。总结起来，这份资料深入探讨了内存系统的关键组件和它们的技术进步，包括DDR家族的不同版本，封装技术的选择，以及这些技术如何影响数据传输速度和系统性能。对于想要深入了解内存技术发展和优化的读者来说，这是一个不可多得的学习资源。

Chapter 12 EVOLUTIONARY DEVELOPMENTS OF DRAM DEVICE ARCHITECTURE 491

for the cacheline sizes of all mainstream processors.

Consequently, different versions of Direct RDRAM

devices had to be designed for error correcting mem-

ory systems and systems that did not require error cor-

rection. At the 64-Mbit density node, 64-Mbit Direct

RDRAM devices with 16-bit-wide data busses were

available alongside 72-Mbit Direct RDRAM devices

with 18-bit-wide data busses. Similarly, 144-, 288-,

and 576-Mbit Direct RDRAM devices were available

alongside 128-, 256-, and 512-Mbit devices in each

density node, respectively. The different versions

of Direct RDRAM devices split the volume demand

for Direct RDRAM devices, providing yet another

obstacle that hindered cost-reduction efforts in

Direct RDRAM memory systems.

Lessons for Future Memory Systems

The Direct RDRAM memory system introduced a

high level of complexity and new cost adders into the

memory system, but the fact that it was coupled to

a relatively low-frequency Pentium III-based system

meant that it did not demonstrate its best-case per-

formance advantage over lower cost SDRAM and DDR

SDRAM memory systems. Consequently, it met a great

deal of resistance and encountered numerous obsta-

cles in its way of reaching high volume production

status, approaching price parity with SDRAM memory

systems and demonstrating a tangible performance

advantage in production systems. Ultimately, the

Direct RDRAM memory system failed to reach com-

modity status. However, the technical challenges

faced by Direct RDRAM memory systems were impor-

tant lessons that Rambus Corp. heeded in the design

of its next-generation high bandwidth memory

system, the XDR memory system.

12.4.3 XDR Memory System

Rambus Corp., having learned valuable lessons

from the drawbacks of the Direct RDRAM memory

system, proceeded to design its next-generation high

bandwidth memory system that avoided many of

the technical pitfalls that hindered acceptance of the

Direct RDRAM memory system. The Extreme Data

Rate (XDR) memory system has been designed to

further increase DRAM device and memory system

signaling rate, yet at the same time to reduce system

design complexity and DRAM device overhead.

Topology

Figure 12.33 illustrates the basic system topol-

ogy of the XDR memory system. The ﬁ gure shows

Intel’s Itanium and IBM’s server-oriented POWER processors do have 128-byte cachelines, but neither system seriously

contemplated such a memory system.

XDR

DRAM 1

XDR

Memory

Controller

16 bits

3.2 Gbps

XDR

DRAM 0

fully

delayed

skewed data

Command and

Address Bus

de-skewed data

term

FIGURE 12.33: Basic topology of the XDR memory system.

492 Memory Systems: Cache, DRAM, Disk

that in the XDR memory system, as in DDRx SDRAM

systems, the command-and-address busses operates

at a relatively lower data rate as compared to the data

bus. In the XDR memory system, the command and

address datapath is a path-length-matched, unidirec-

tional datapath that the XDR memory controller uses

to broadcast command and address information to

DRAM devices. Figure 12.33 also shows that the XDR

controller uses FlexPhase to do skew compensation

on the datapath—removes skew on read data coming

into the controller and adds skew to ensure that write

data reaches DRAM device interface in sync.

Device Architecture

Figure 12.34 illustrates the device organization

of an XDR device. The XDR DRAM device is char-

acterized by numerous features that distinguish it

from the Direct RDRAM device. For example, the

XDR DRAM device has a prefetch length of 16, so

the minimum burst length is 16. However, the XDR

device architecture has been designed with vari-

able device data bus width control so that a device

may be conﬁ gured with a data bus width as low as 1

bit. Consequently, the minimum granularity of data

movement in such a device may be as small as 16

bits. Figure 12.34 also shows that the XDR device

is internally organized into two different, odd and

even, bank sets.

Finally, Figure 12.34 shows that the XDR device

differs from the Direct RDRAM device in that unlike

the Direct RDRAM device, the XDR DRAM device has

a common command bus that is used by row access

commands as well as column access commands.

Moreover, unlike the Direct RDRAM device, the XDR

DRAM device does not have a write buffer. Instead,

it relies on the differing bank sets and an intelligent

controller to alleviate the write-to-read data bus

turnaround issue.

Signaling

Figure 12.35 shows the octal data rate signaling

system that Rambus Corp. introduced with the XDR

memory system. In this signaling system, a relatively

slow master clock signal (400~800 MHz) is shared by

both the memory controller and the DRAM device. The

DRAM device and the memory controller use current

mirrors to transmit differential signals that are locked

in-phase with the system clock signal, but operate at

four times the frequency of the system clock signal.

Data is transmitted on both edges of the signal, so 8

1-bit symbols per pin pair are transmitted in every

clock cycle. The low voltage swing, point-to-point,

differential signaling enables high bandwidth in com-

modity ASIC and DRAM processor technologies at the

cost of higher power consumption.

FlexPhase

In the XDR memory system, Rambus Corp. uses

a system of bit-adjustable DLL circuitry to remove

bit-to-bit signal skew from the high-speed parallel

data bus. This system of bit-adjustable DLL circuitry

is referred to as FlexPhase. Figure 12.35 shows how

Rambus uses the FlexPhase circuit to account for dif-

ferences in signal ﬂ ight time. FlexPhase takes care

of data-to-data skew, and it can be recalibrated to

lock in new phase differentials to account for ther-

mal drifts between cold and warm systems. Figure

12.35 shows that the FlexPhase circuitry is placed

in the controller interface. In this manner, the Flex-

Phase technology removes the path-length matching

requirement from the XDR memory system without

increasing the cost of the DRAM device. In this case,

the additional cost is paid for in terms of increased

controller sophistication.

XDR Early Read After Write

To counter the various drawbacks of a write buffer

in Direct RDRAM devices, Rambus did not include

write buffers in the design of its next-generation,

high-performance XDR DRAM device. Instead, XDR

DRAM devices are architected to support a feature

that Rambus refers to as the Early Read After Write

(ERAW) feature. Essentially, XDR devices avoid the

large write-to-read command overhead by using sepa-

rate internal paths for banks separated into odd and

even sets. In this organization, a read command can

proceed in parallel with a write command, as long as

the read and write commands are directed to banks in

494 Memory Systems: Cache, DRAM, Disk

different bank sets. Figure 12.36 shows that although

the write-to-r

ead turnaround overhead still occupies

several cycles, the overhead is much smaller than if the

write and read commands are issued to the same set

of banks.

12.5 Low Latency

The proliferation of low-cost commodity DRAM

devices means that high-speed, low-latency SRAM

devices have been pushed into increasingly small

niches as design engineers seek to use DRAM devices

wherever they can to reduce system cost. However,

even as DRAM devices replace SRAM in more

and more applications, the desire for lower-than-

commodity-DRAM latency characteristics remains.

Consequently, DRAM device manufacturers have

been developing specialty low-latency DRAM devices

as semi-commodity, moderately low-latency replace-

ments for SRAM replacement application. Two fami-

lies of DRAM devices, the Reduced Latency DRAM

(RLDRAM) and Fast Cycle DRAM (FCRAM), have

been designed speciﬁ cally to target the low-latency

SRAM replacement market.

12.5.1 Reduced Latency DRAM (RLDRAM)

RLDRAM is a low-latency DRAM device with ran-

dom access latency as low as 10–12 ns and row cycle

times as low as 20 ns. The ﬁ rst-generation RLDRAM

device was designed by Inﬁ neon to meet the

demands of the market for networking equipment.

Subsequently, Micron was brought in as a partner to

co-develop RLDRAM and provide a second source.

However, Inﬁ neon has since abandoned RLDRAM

development, and Micron proceeded ahead to

develop the second-generation RLDRAM II. RLDRAM

and RLDRAM II were designed for use in embedded

applications. Primarily, RLDRAM is designed for the

network market. However, it may also be used for

other applications where cost is less of a concern,

low latency is a highly desirable feature, and smaller-

than-commodity-DRAM capacity is not an issue. For

example, RLDRAM may be used as a large lookup table

or a large off-chip cache. RLDRAM has been designed

with an SRAM-like mentality in that it is designed for

SRAM-like random access to any part of the DRAM

device; row address and column addresses are com-

bined together and sent as a single access command.

400 MHz system clock signal

3.2 Gbps Data Rate

PLL

latch

3.2 Gbps

Data Rate

3.2 Gbps

Data Rate

latch

FlexPhase

controller

interface

DRAM

device

FIGURE 12.35: Octal data rate signaling using per-bit FlexPhase de-skewing and PLL in an XDR memory system.

Chapter 12 EVOLUTIONARY DEVELOPMENTS OF DRAM DEVICE ARCHITECTURE 495

Column Cmd

Data Bus

CWD

(Write delay)

6 knaB

Control

logic

noitanimret

)RW( xumeD htdiW cimanyD

mretV

t/61

elcyC

ksaM etyB

)DR( xumeD htdiW cimanyD

t/61

elcyC

61 x 61

Even Bank

Array

Odd Bank

Array

Write Data

Read Data

Separate internal

data busses to

odd and even

bank sets

time

Read commands can proceed

and move data to the I/O gating

structure in parallel to a write

command moving data into

the device, if the respective data

movements are made to different

banks in different bank sets.

Array 0

Bank 0

Array 1

Array 7

Bank 1

Bank 7

Sense Amp Array

16 x 16 * 2

Sense Amp Array

16 x 16 * 2

xum 1:61

xumeD 61:1

16 x 16

12.5.2 Fast Cycle DRAM (FCRAM)

In contrast to RLDRAM, Fujitsu and Toshiba’s

FCRAM achieves low-latency data access by seg-

menting the data array into multiple subarrays, only

one of which is driven during a row-activation com-

mand. The sub-row activation process effectively

decreases the size of an array and improves access

time. Unlike RLDRAM, FCRAM was designed with a

DDRx SDRAM-like mentality, where row access com-

mands and column access commands are sent sepa-

rately, and the FCRAM command set was designed

speciﬁ cally to mimic the DDRx SDRAM command

set. The purpose of the commonality is to enable

controller designs that can use either FCRAM or

commodity DDRx SDRAM devices. Finally, differing

from RLDRAM devices, FCRAM was designed with a

DIMM speciﬁ cation.

12.6 Interesting Alternatives

12.6.1 Virtual Channel Memory (VCDRAM)

Virtual channel adds a substantial SRAM cache to

the DRAM that is used to buffer large blocks of data

(called segments) that might be needed in the future.

The SRAM segment cache is managed explicitly by

the memory controller. The design adds a new step

in the DRAM-access protocol: a row activate opera-

tion moves a page of data into the sense ampliﬁ ers;

“prefetch” and “restore” operations (data-read and

FIGURE 12.36: Read following write in an XDR DRAM device that supports ERAW.

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