LPC11E68: 32位低成本ARM Cortex-M0+ MCU，详解特性与优势

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LPC11E6X系列是恩智浦(NXP)针对低成本应用开发的32位ARM Cortex-M0+微控制器家族，其最大工作频率可达50MHz。这款MCU集成了高效能、易用的Cortex-M0+内核，具备两阶段流水线和快速单周期I/O访问能力，旨在提供出色的功耗管理和性能表现。该系列MCU的主要特点包括： 1. **存储器配置**：支持高达256KB的闪存内存、4KB的EEPROM以及36KB的静态随机存取存储器(SRAM)，能满足基本的数据存储需求。 2. **外设组件**： - DMA控制器：用于提高数据传输速度和效率。 - CRC引擎：内置循环冗余校验(CRC)功能，用于数据完整性校验。 - I2C接口：提供两个接口，支持串行通信。 - USARTs：多达五个全双工通用异步收发传输器，适用于多种通信协议。 - SSP接口：简单串行接口，支持串行通信。 - PWM/定时器子系统：包含六个可配置的多用途定时器，具有灵活的定时和脉宽调制功能。 - 实时钟(RTC)：确保时间保持准确。 - 12位模拟到数字转换器(ADC)：用于信号采集。 - 温度传感器：集成传感器提供环境监测能力。 - 功能可配置的I/O端口：适应多种应用场景，最多可有80个通用输入/输出引脚。 3. **调试与开发支持**：支持Serial Wire Debug (SWD)和边界扫描模式的JTAG，便于硬件调试和芯片级编程。 4. **系统特性**： - ARM Cortex-M0+处理器，具有r0p1版本，能提供单周期乘法和高速I/O访问。 - 内置嵌套向量中断控制器(NVIC)，有效管理中断处理。 - 高速存储器总线(AHB)多层矩阵，提升数据传输性能。 - 系统时钟定时器，确保精确的时间基准。此外，文档还提到在第18部分“参考资料”中提供了关于LPC11E6X系列更详细的补充资料和技术指南，供开发者深入学习和参考。通过这些特性，LPC11E6X系列成为低成本应用的理想选择，尤其适合对功耗控制和实时性能有较高要求的项目。

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Product data sheet Rev. 1.2 — 21 May 2014 15 of 89

NXP Semiconductors

LPC11E6x

32-bit ARM Cortex-M0+ microcontroller

PIO2_2

12 16 21

[6]

I; PU IO PIO2_2 — General-purpose digital input/output pin.

O U3_RTS

— Request To Send output for USART3.

IO U3_SCLK — Serial clock input/output for USART3 in

synchronous mode.

O SCT0_OUT1 — SCTimer0/PWM output 1.

PIO2_3

19 24 36

[6]

I; PU IO PIO2_3 — General-purpose digital input/output pin.

I U3_RXD — Receiver input for USART3.

O CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO2_4

21 27 41

[6]

I; PU IO PIO2_4 — General-purpose digital input/output pin.

O U3_TXD — Transmitter output for USART3.

O CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO2_5

91115

[6]

I; PU IO PIO2_5 — General-purpose digital input/output pin.

I U3_CTS

— Clear To Send input for USART3.

I SCT0_IN1 — SCTimer0/PWM input 1.

PIO2_6

-2537

[6]

I; PU IO PIO2_6 — General-purpose digital input/output pin.

O U1_RTS

— Request To Send output for USART1.

IO U1_SCLK — Serial clock input/output for USART1 in

synchronous mode.

I SCT0_IN2 — SCTimer0/PWM input 2.

PIO2_7

20 26 40

[6]

I; PU IO PIO2_7 — General-purpose digital input/output pin.

IO SSP0_SCK — Serial clock for SSP0.

O SCT0_OUT2 — SCTimer0/PWM output 2.

PIO2_8

--2

[6]

I; PU IO PIO2_8 — General-purpose digital input/output pin.

I SCT1_IN0 — SCTimer1/PWM input 0.

PIO2_9

--3

[6]

I; PU IO PIO2_9 — General-purpose digital input/output pin.

I SCT1_IN1 — SCTimer1/PWM_IN1

PIO2_10

--16

[6]

I; PU IO PIO2_10 — General-purpose digital input/output pin.

O U4_RTS

— Request To Send output for USART4.

IO U4_SCLK — Serial clock input/output for USART4 in

synchronous mode.

PIO2_11

--24

[6]

I; PU IO PIO2_11 — General-purpose digital input/output pin.

I U4_RXD — Receiver input for USART4.

PIO2_12

--25

[6]

I; PU IO PIO2_12 — General-purpose digital input/output pin.

O U4_TXD — Transmitter output for USART4.

PIO2_13

--26

[6]

I; PU IO PIO2_13 — General-purpose digital input/output pin.

I U4_CTS

— Clear To Send input for USART4.

PIO2_14

--27

[6]

I; PU IO PIO2_14 — General-purpose digital input/output pin.

I SCT1_IN2 — SCTimer1/PWM input 2.

Table 3. Pin description

Pin functions are selected through the IOCON registers. See Table 2

for availability of USART4 pin functions.

Symbol

LQFP48

LQFP64

LQFP100

Reset

state

[1]

Type Description of pin functions

Product data sheet Rev. 1.2 — 21 May 2014 16 of 89

NXP Semiconductors

LPC11E6x

32-bit ARM Cortex-M0+ microcontroller

PIO2_15

-3249

[6]

I; PU IO PIO2_15 — General-purpose digital input/output pin.

I SCT1_IN3 — SCTimer1/PWM input 3.

PIO2_16

--50

[6]

I; PU IO PIO2_16 — General-purpose digital input/output pin.

O SCT1_OUT0 — SCTimer1/PWM output 0.

PIO2_17

--51

[6]

I; PU IO PIO2_17 — General-purpose digital input/output pin.

O SCT1_OUT1 — SCTimer1/PWM output 1.

PIO2_18

-3352

[6]

I; PU IO PIO2_18 — General-purpose port 2 input/output 18.

O SCT1_OUT2 — SCTimer1/PWM output 2.

PIO2_19

-3657

[6]

I; PU IO PIO2_19 — General-purpose port 2 input/output 19.

O SCT1_OUT3 — SCTimer1/PWM output 3.

PIO2_20 - - 75

[6]

I; PU IO PIO2_20 — General-purpose port 2 input/output 20.

PIO2_21 - - 76

[6]

I; PU IO PIO2_21 — General-purpose port 2 input/output 21.

PIO2_22 - - 77

[6]

I; PU IO PIO2_22 — General-purpose port 2 input/output 22.

PIO2_23 - - 1

[6]

I; PU IO PIO2_23 — General-purpose port 2 input/output 23.

RSTOUT

- - 88

[6]

IA IO Internal reset status output.

RTCXIN 48 1 5

[2]

- - RTC oscillator input. This input should be grounded if the

RTC is not used.

RTCXOUT 1 2 6

[2]

- - RTC oscillator output.

VREFP 34 47 73 - - ADC positive reference voltage. If the ADC is not used, tie

VREFP to V

VREFN 35 48 74 - - ADC negative voltage reference. If the ADC is not used, tie

VREFN to V

DDA

40 53 84 - - Analog voltage supply. V

DDA

should typically be the same

voltages as V

but should be isolated to minimize noise

and error. V

DDA

should be tied to V

if the ADC is not

used.

44,

58,

10,

34,

92,

14,

71,

54,

- - Supply voltage to the internal regulator and the external

rail.

VBAT 47 63 99 - - Battery supply. Supplies power to the RTC. If no battery is

used, tie VBAT to VDD.

SSA

41 54 85 - - Analog ground. V

SSA

should typically be the same voltage

as V

but should be isolated to minimize noise and error.

SSA

should be tied to V

if the ADC is not used.

43,

57,

91,

11,

53,

- - Ground.

n.c. - - 39 Not connected.

n.c. - - 38 Not connected.

Table 3. Pin description

Pin functions are selected through the IOCON registers. See Table 2

for availability of USART4 pin functions.

Symbol

LQFP48

LQFP64

LQFP100

Reset

state

[1]

Type Description of pin functions

Product data sheet Rev. 1.2 — 21 May 2014 17 of 89

NXP Semiconductors

LPC11E6x

32-bit ARM Cortex-M0+ microcontroller

[1] Pin state at reset for default function: I = Input; O = Output; AI = Analog Input; PU = internal pull-up enabled; IA = inactive, no

pull-up/down enabled;

F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption.

[2] Special analog pad.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as analog input, digital section of the pad is disabled and the pin is not 5 V tolerant; includes digital, programmable

filter.

[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as analog input, digital section of the pad is disabled and the pin is not 5 V tolerant; includes digital input glitch filter.

WAKEUP pin. The wake-up pin function can be disabled and the pin can be used for other purposes if the RTC is enabled for waking up

the part from Deep power-down mode.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes

high-current output driver.

[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[7] I

C-bus pin compliant with the I

C-bus specification for I

C standard mode, I

C Fast-mode, and I

C Fast-mode Plus. The pin requires

an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines.

Open-drain configuration applies to all functions on this pin.

[8] 5 V tolerant pad. RESET

functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up

from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

[9] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog crystal

oscillator connections. When configured for the crystal oscillator input/output, digital section of the pad is disabled and the pin is not 5 V

tolerant; includes digital, programmable filter.

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