IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-Q, NO. 6, DECEMBER1974
[51 R. A. Stehlin and G. W. Niemann, “Complementary tran-
sistor-transistor logic (CTzL)—an approach to high-speed
micropower logic,”
IEEE J. Solid-State Circuits, vol. SC-7,
pp. 153–160, Apr. 1972.
Paul C. Davis (S’64)-M’61) was born in
Glenville, W. Vs., on March 14, 1937. He
received the B.S.E E. degree from West
Virginia University, Morgantown, in 1959,
the M.S. degree from Massachusetts Insti-
tute of Technology, Cambridge, in 1961, and
the Ph.D. degree in electrical engineering
from Lehigh University, Bethlehem, Pa., in
1968.
He has been a Teaching Assistant at
M.I.T. and served two years as an army
officer in the Ordnance Guided Missile School, Huntsville, Ala.
In 1962 he became a Member of the Technical Staff, Bell Labora-
tories, Reading, Pa. He has been engaged in characterization
and modeling of transistors and in the design of linear and digital
integrated circuitry.
Dr. Davis is a member of Eta KapDa Nu and Tau Beta Pi, and
an associate member of Sigma Xi. “ -
Relationship Between
347
Stanley
F. Moyer was born in Hamburg,
Pa., on September 8, 1931. He graduated
from Capitol Radio Engineering Institute,
Washington, D.C. in 1956. He has also at-
tended Albright College, Reading, Pa.j and
Lafayette College, Easton, Pa.
In 1956 he joined Bell Laboratories, Read-
ing, Pa., where he has worked on the
development of germanium diffused base
transistors, silicon transistors, and field-
effect
transistors. Since 1966, he has worked
on the development of silicon monolithic integrated circuits.
Veikko R. Saari was born in Brooklyn, N.Y.,
on April 24, 1928. He received the B.S. and
M.S. degrees in physics from the University
of Minnesota, Minneapolis, in 1951 and
1956, respectively.
Since 1956 he has been working on the
design of solid-state circuits at Bell Lab-
oratories, Holmdel, N.J.
Mr. Saari is a member of the American
Association of Physics Teachers.
Frequency Response and
Settling
‘Time of Oper;tion~ Amplifiers
B. YESHWANT KAMATH, STUDENT MEMBER, IEEE, ROBERT G. MEYER, MEMBER, IEEE, AND
PAUL R. GRAY, MEMBER, IEEE
Abstracf—The effects of pole-zero pairs (doublets) on the fre-
quency response and settling time of operational amplifiers are
explored using analytical techniques and computer simulation. It
is shown that doublets which produce only minor changes in circuit
frequency response can produce major changes in settling time. The
importance of doublet spacing and frequency are examined. It is
shown that settling time always improves as doublet spacing is
reduced whereas the effect of. doublet frequency is different for
0.1 and 0.01 percent error bands. Finally it is shown that simple
analytical formulas can be used to estimate the influence of fre-
quency doublets on amplifier settling time.
I. INTRODUCTION
I
~ MANY
applications of operational amplifiers, the
settling time is an important parameter [1]. The
settling time is the time taken for the output of the
amplifier to settle to within 0.1 or 0.01 percent after the
Manuscript received May 13, 1974; revised August 8, 1974. This
work was supported by the Joint Services Electronics Program
under Contract F44620-71-C-@187.
The authors are with the Department of Electrical Engineering
and Computer Sciences and the Electronics Research Laboratory,
IJniversity of California, Berkeley, Calif. 9472Y3.
application of an input step. This test is usually done in
a unity-gain configuration with a 1O-V step input and
thus the error bands on the output are 10 and 1 mV, re-
spectively, for 0.1 and 0.01 percent accuracy. These tests
are important in specifying the operational amplifier for
use in such applications as A/D and D/A converters.
The settling time of an amplifier is composed of two
distinct periods [1]. The first period is called the slew
time during which the amplifier output makes the transi-
tion from the original output voltage to the vicinity of
the new value. During this period the amplifier acts in a
grossly nonlinear fashion and the length of this period
is generally determined by the current available to charge
the amplifier compensation capacitance. The second por-
tion of the settling time is the period after slew limiting
when the amplifier output is near its final value and the
circuit acts in a quasi-linear fashion. It has been shown
[2], [3] that this period is significantly affected by the
presence of pole-zero pairs (called doublets) in the am-
plifier transfer function. In high-speed operational ampli-
fiers, the slew time can be very short and this second
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