MFRC522芯片：13.56MHz非接触式读写器

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"MFRC522是一款专用于13.56MHz频段无接触式读写器的集成电路芯片，支持ISO14443A/MIFARE®模式。这款芯片集成了发送和接收部分，能够直接驱动读写器天线与符合ISO/IEC14443A/MIFARE®标准的卡片和应答器进行通信，无需额外的主动电路。其接收部分包含强大的解调和解码电路，确保信号处理的稳定高效。MFRC522的数字部分处理完整的ISO/IEC14443A帧结构及错误检测（奇偶校验和CRC）。此外，它还支持MIFARE® Classic产品，如MIFARE® Standard，并能实现双向最高848kbit/s的MIFARE®高速无接触通信。MFRC522提供了多种主机接口，包括SPI接口、类似于RS232的串行UART（根据电源电压设置电平）以及I2C接口。" MFRC522芯片是IC卡读卡技术中的关键组件，主要用于构建无接触式RFID系统。它的工作频率为13.56MHz，符合ISO14443A标准，这使得它能够与广泛使用的MIFARE®系列卡片兼容。MIFARE®技术是NXP Semiconductors开发的一种非接触式智能卡标准，常见于公共交通、门禁控制和支付系统等领域。该芯片的发射部分设计用于驱动专为无接触通信设计的读写器天线，而接收部分则包含了高效率的信号解调和解码功能，确保了与MIFARE®卡片和应答器之间的可靠通信。MFRC522芯片的数字逻辑部分负责执行ISO/IEC14443A规定的帧结构和错误检测机制，从而保证数据传输的准确性和完整性。在通信速度方面，MFRC522芯片支持高达848kbit/s的MIFARE®高速模式，这远超过了许多其他同类产品的速度，使得数据交换更加迅速。此外，MFRC522还具备灵活的主机接口选择，可以适应不同的应用需求，如SPI接口适用于高速、低延迟的通信，UART接口则提供了一个与标准RS232兼容的串行通信选项，而I2C接口则常用于资源有限的系统中。 MFRC522是一款高度集成、功能强大的无接触式读卡芯片，适用于需要高效、可靠且具有多种通信选项的RFID系统设计。无论是在安全支付、身份验证还是物联网(IoT)应用中，MFRC522都是构建高性能无接触式读卡解决方案的理想选择。

Product data sheet Rev. 3.2 — 22 May 2007 16 of 109

NXP Semiconductors

MFRC522

Contactless Reader IC

9.2.1.4 DivIEnReg

Control bits to enable and disable the passing of interrupt requests.

9.2.1.5 CommIRqReg

Contains Interrupt Request bits.

Table 13: DivIEnReg register (address 03h); reset value: 00h

Bit 7 6 5 4 3 2 1 0

Symbol IRQPushPull - MfinActIEn - CRCIEn -

Access

Rights

r/w RFU r/w RFU r/w RFU

Table 14: Description of DivIEnReg bits

Bit Symbol Description

7 IRQPushPull Set to logic 1, the pin IRQ works as standard CMOS output pad.

Set to logic 0, the pin IRQ works as open drain output pad.

6 to 5 - Reserved for future use.

4 MfinActIEn Allows the MFIN active interrupt request to be propagated to pin IRQ.

3 - Reserved for future use.

2 CRCIEn Allows the CRC interrupt request (indicated by bit CRCIRq) to be

propagated to pin IRQ.

1 to 0 - Reserved for future use.

Table 15: CommIRqReg register (address 04h); reset value: 14h

Bit 7 6 5 4 3 2 1 0

Symbol Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq

Access

Rights

wdydydy dy dy dydy

Table 16: Description of CommIRqReg bits

All bits in the register CommIRqReg shall be cleared by software.

Bit Symbol Description

7 Set1 Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg

are set.

Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg

are cleared.

6 TxIRq Set to logic 1 immediately after the last bit of the transmitted data was sent out.

5 RxIRq Set to logic 1 when the receiver detects the end of a valid data stream.

If the bit RxNoErr in register RxModeReg is set to logic 1, Bit RxIRq is only set

to logic 1 when data bytes are available in the FIFO.

4 IdleIRq Set to logic 1, when a command terminates by itself e.g. when the

CommandReg changes its value from any command to the Idle Command.

If an unknown command is started, the CommandReg changes its content to

the idle state and the bit IdleIRq is set. Starting the Idle Command by the

μ-Controller does not set bit IdleIRq.

3 HiAlertIRq Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to

HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit

Set1.

Product data sheet Rev. 3.2 — 22 May 2007 18 of 109

NXP Semiconductors

MFRC522

Contactless Reader IC

9.2.1.7 ErrorReg

Error bit register showing the error status of the last command executed.

[1] Command execution will clear all error bits except for bit TempErr. A setting by software is impossible.

Table 19: ErrorReg register (address 06h); reset value: 00h

Bit 7 6 5 4 3 2 1 0

Symbol WrErr TempErr - BufferOvfl CollErr CRCErr ParityErr ProtocolErr

Access

Rights

rrRFUr rrr r

Table 20: Description of ErrorReg bits

Bit Symbol Description

7 WrErr Set to logic 1, when data is written into the FIFO by the host during the

MFAuthent command or if data is written into the FIFO by the host

during the time between sending the last bit on the RF interface and

receiving the last bit on the RF interface.

6 TempErr

[1]

Set to logic 1, if the internal temperature sensor detects overheating.

In this case, the antenna drivers are switched off automatically.

5 - Reserved for future use.

4 BufferOvfl Set to logic 1, if the host or a MFRC522’s internal state machine (e.g.

receiver) tries to write data into the FIFO buffer although the FIFO

buffer is already full.

3 CollErr Set to logic 1, if a bit-collision is detected. It is cleared automatically at

receiver start-up phase. This bit is only valid during the bitwise

anticollision at 106 kbit/s. During communication schemes at 212,

424 and 848 kbit/s this bit is always set to logic 0.

2 CRCErr Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the

CRC calculation fails. It is cleared to logic 0 automatically at receiver

start-up phase.

1 ParityErr Set to logic 1, if the parity check has failed. It is cleared automatically

at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE

communication at 106 kbit/s.

0 ProtocolErr Set to logic 1, if one out of the following cases occur:

• Set to logic 1 if the SOF is incorrect. It is cleared automatically at

receiver start-up phase. The bit is only valid for 106 kbit/s.

• During the MFAuthent Command, bit ProtocolErr is set to logic 1,

if the number of bytes received in one data stream is incorrect.

剩余108页未读，继续阅读

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