LPC43xx ARM Cortex-M4/M0 双核微控制器用户手册

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"UM10503 LPC43xx ARM Cortex-M4/M0 双核微控制器用户手册" 本手册详细介绍了NXP公司生产的LPC43xx系列微控制器，这是一个基于ARM Cortex-M4和Cortex-M0双核心架构的处理器。该系列包括多个型号，如LPC4350、LPC4330、LPC4320等，涵盖了广泛的性能和功能选项。LPC43xx系列微控制器集成了多种高级特性，使其在嵌入式系统设计中具有广泛的应用潜力。关键词涉及到LPC43xx系列的不同型号以及其核心技术，如SPIFI（SPI闪存接口）、状态配置定时器（SCT）、USB、以太网等。这些技术是LPC43xx微控制器的关键组成部分，提供了高速数据传输、灵活的定时控制、网络连接和存储扩展等功能。文档的修订历史显示，手册在2013年1月25日更新到了1.6版本，主要改进了几个关键点，包括： - 清晰化了SGPIO（系统GPIO）与DMA（直接内存访问）的连接关系，图8和图9进行了修正。 - 纠正了图1和图2中SGPIO的位置。 - 在DMA主控0中增加了SGPIO，见第19.4节和第18.4.1节。 - 更新了GPIO组中断在电源关闭模式下的唤醒情况，现在只支持从睡眠模式唤醒，见第17.3.2节。 - 将“支持的QSPI设备”部分移动到第五章“LPC43xx引导ROM”。 - 在第二十二章“SPIFI寄存器映射和寄存器描述”中新增了SPIFI的相关信息。 LPC43xx微控制器的特性包括但不限于： 1. 双核心架构：结合高性能的Cortex-M4（带浮点单元）和节能的Cortex-M0，适用于需要高效能和低功耗并存的应用场景。 2. SPIFI接口：提供高速的SPI闪存访问，提高了系统启动速度和程序执行效率。 3. SCT模块：这是一个高度可配置的定时器，可以实现复杂的时序控制，满足多样化应用需求。 4. USB接口：内置USB控制器，支持USB 2.0全速和低速设备，便于设备间的数据交换。 5. 以太网接口：集成以太网MAC，可以实现网络通信功能。 NXP LPC43xx系列微控制器是一套功能强大的嵌入式解决方案，适用于需要高处理能力和低功耗的嵌入式应用，如工业控制、物联网设备、消费电子产品等。用户手册提供详尽的技术信息，帮助开发者充分利用这些功能进行系统设计。

User manual Rev. 1.6 — 25 January 2013 16 of 1316

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Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process

The basic IPC features are:

• The ARM Cortex-M4 initializes the ARM Cortex-M0 system.

• The ARM Cortex-M4 communicates with the ARM Cortex-M0 system via a command

queue.

• The message queues are located in the ARM Cortex-M4 address space because the

ARM Cortex-M4 can be blocked from access to the ARM Cortex-M0 hardware

subsystem.

2.5.1 IPC queues

The ARM Cortex-M4 has an output command queue and an input message queue. A

queue is defined by four registers:

1. queue start address

2. queue end address

3. write pointer

4. read pointer

The ARM Cortex-M4 initializes these four registers. These registers reside in the same

shared SRAM as the queues to ensure that data and registers changes are synchronous.

Their location is static and known up front by the ARM Cortex-M0.

Messages are passed through queues using cyclic buffers. A queue is filled with

commands or messages from start to end address. When a buffer pointer points beyond

the end address it wraps around to the start address. When the read pointer is equal to

the write pointer, the queue can be either empty or completely full. To avoid this ambiguity

the queue shall never be filled completely. The minimum queue size is thus 3 words (the

longest command/message +1 word). An equal write and read pointer will indicate an

empty queue.

The command queue is filled by the ARM Cortex-M4 and emptied by the ARM Cortex-M0;

the write pointer is advanced by the ARM Cortex-M4 every time it adds a new command

to the queue. The read pointer is advanced by the ARM Cortex-M0 every time it removes

a command from the queue.

The message queue is filled by the ARM Cortex-M0 and emptied by the ARM Cortex-M4;

the write pointer is advanced by the ARM Cortex-M0 every time it adds a new message to

the queue. The read pointer is advanced by the ARM Cortex-M4 every time it removes a

message from the queue.

When a new command or message has been added to the queue and the write pointer

had been updated, an interrupt is raised to the other processor. The commands are

acknowledged by a return message (accept or fail).

The ARM Cortex-M4 and ARM Cortex-M0 only have one IPC write and one IPC read task.

If multiple instances exist then a local arbiter shall ensure that all write and read

operations are atomic; after data has been written (read) the write (read) pointer is

updated before another write (read) operation can start.

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UM10503

Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process

It is the responsibility of the process writing to a queue making sure that the queue is not

filled completely; before loading a new item the process should confirm that the write

pointer will not be equal to, or overtake the read pointer and will leave at least one free

space. On the other hand the receiving side shall promptly process and remove items

from the queue.

No explicit error handling is performed. It is assumed that the ARM Cortex-M0 will always

respond to a ARM Cortex-M4 command.

2.5.2 Protocol

The ARM Cortex-M0 is used a co-processor to off-load the ARM Cortex-M4 and to

perform serial IO tasks. The ARM Cortex-M4 should be able to initialize tasks executed on

the ARM Cortex-M0. The ARM Cortex-M0 should be able to signal to the ARM Cortex-M4

when these tasks have completed or failed. This is done by issuing commands from ARM

Cortex-M4 to ARM Cortex-M0, where the ARM Cortex-M0 responds with messages. This

command and message interface resembles a hardware register level interface with

command and status registers.

The ARM Cortex-M4 issues 32-bit commands to the ARM Cortex-M0. Each command

starts with a 16-bit ID that defines which task is referred to. The LSBit indicates the

command type. A Write command is followed by a 32-bit operand. When a new command

is available, the ARM Cortex-M4 signals this to the ARM Cortex-M0 by raising an

interrupt.

The ARM Cortex-M0 return 32-bit messages to the ARM Cortex-M4. A messages starts

with a 16-bit ID that indicates which tasks the message refers to. The LSByte indicates the

message type. A Read response message is followed by the 32-bit read operand. When a

new message is available, the ARM Cortex-M0 signals this to the ARM Cortex-M4 by

raising an interrupt.

Small data transfers can be performed by the single 32-bit data read, CMD_RD_ID, and

write, CMD_WR_ID, commands. These commands use a 3-Byte addressing scheme to

support an argument space of 212 = 4096 32-bit words. Large data transfers can be more

efficiently handled using pointers.

Also higher level interfaces using API calls will typically use indirect, pointer based, reads

and writes.

When multiple tasks are running concurrently the ID is used to distinguish commands and

messages belonging to a certain task. A global command parser should be used to the

kick off commands to the tasks running on the ARM Cortex-M0.

The same holds true for the ARM Cortex-M4 side, a global message parser channels

back messages to the task dispatchers running on the ARM Cortex-M4 side.

Table 5. Command list

Command Bit mask Description

CMD_RD_ID 0xTTTT.PPP0 read 32 bit WORD with argument ID=0xPPP

from the task with ID = 0xTTTT

CMD_WR_ID 0xTTTT.PPP1, WORD write 32 bit WORD with argument ID=0xPPP to

the task with ID = 0xTTTT

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Chapter 2: LPC43xx ARM Cortex-M0 co-processor and Inter- Process

2.5.3 Example

Assume a certain task with ID 0x1234 should be executed by the ARM Cortex-M0. For

example, read data from a register level interface controlled by the ARM Cortex-M0. Text

in bold indicates a register.

The registers can either be located in the ARM Cortex-M0 SRAM, for more deterministic

access times, or in shared SRAM. If the ARM Cortex-M0 SRAM is used, then the register

data needs to be copied at initialization time. This copying takes time. The ARM

Cortex-M4 can poll a status register to determine when the transfer has finished.

The ARM Cortex-M4 initializes the command and message queues by loading the start-

and end addresses and write and read pointers.

Then the ARM Cortex-M4 loads the register values in a reserved area in common SRAM

memory. An alternative approach is that the ARM Cortex-M4 writes register per register,

however this requires more communication overhead than loading all data in one go.

Once all data has been set up, the ARM Cortex-M0 task can be started.

Table 6. Message list

Message Bit mask Description

MSG_SRV_ID 0xTTTT.SS00 ARM Cortex-M0 request servicing for the task

with ID = 0xTTTT. The service type is coded in

bytes SS. The meaning of SS is proprietary per

task. SS=0x00 means the task has finished.

MSG_RD_ID 0xTTTT.PPP1, VALUE ARM Cortex-M0 responds with VALUE to a read

of WORD with argument ID=0xPPP* from the

task with ID = 0xTTTT.

MSG_RD_STS_ID 0xTTTT.PPPR ARM Cortex-M0 response to a read of WORD

with argument ID=0xPPP* from the task with ID

= 0xTTTT fails. Cause of the failure is coded in

R; R = 2...4

2 = invalid argument

3 = reserved

4 = reserved

MSG_WR_STS_ID 0xTTTT.PPPW ARM Cortex-M0 response to a write with

argument ID=0xPPP* from the task with ID =

0xTTTT. Response is coded in W; W = 5...7

5 = write was successful

6 = write failed

7 = reserved

Table 7. Command responses

Command Possible responses Description

CMD_RD_ID MSG_RD_ID, VALUE read acknowledged

MSG_RD_STS_ID read failed

CMD_WR, WORD MSG_WR_STS_ID write is acknowledged as a success or failure

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