HCS500：加密滚动码解码器，支持I2C，广泛应用于汽车安全系统

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HCS500是一款专为滚动码解码设计的高安全性的芯片，由Microchip Technology Inc.在2011年推出。这款芯片的核心特性在于其强大的加密功能，包括对制造商代码和加密密钥的存储加密，确保了数据的安全性。HCS500最多能学习并处理多达七个发射器，采用了先进的KEELOQ®代码跳跃技术，提供了正常和安全两种学习模式，增强了系统的防伪和抗干扰能力。 HCS500的工作范围广泛，可在3.0V至5.5V电压下稳定运行，内置振荡器确保了其在各种应用中的可靠性能。它具有自动比特检测功能，简化了系统集成过程。作为一款独立的解码芯片集，HCS500配备外部EEPROM用于存储发射器数据，提供了一个同步串行接口，便于与单片机和其他设备通信。内部还包含1Kbit用户EEPROM，用于存储定制参数或用户数据。该芯片适用于多种高安全性的应用场景，如汽车远程钥匙进入系统、防盗报警系统、车载电子防盗系统、车库门和电子门锁控制系统、身份验证令牌以及家庭或商业用的防盗报警系统。它兼容各种配置的KEELOQ编码器和应答器，这些设备须满足特定设置，如PWM调制格式（1/3-2/3）、脉冲宽度范围（100us到400us）、TE（传输时间）标准、10x TE Header、28位序列号、16位同步计数器以及特定的歧视位和码字长度（66至69位）。 HCS500凭借其高级加密技术和广泛的兼容性，为各种需要高度安全和可靠远程控制的系统提供了理想的解决方案。它的紧凑型8-pin DIP/SOIC封装使得它在空间受限的设计中也易于集成，是现代智能安防和自动化领域的重要组成部分。

HCS500

3.5 Synchronization with Decoder

(Evaluating the Counter)

The KEELOQ technology patent scope includes a

sophisticated synchronization technique that does not

require the calculation and storage of future codes. The

technique securely blocks invalid transmissions while

providing transparent resynchronization to transmitters

inadvertently activated away from the receiver.

Figure 3-3 shows a 3-partition, rotating synchronization

window. The size of each window is optional but the

technique is fundamental. Each time a transmission is

authenticated, the intended function is executed and

the transmission's synchronization counter value is

stored in EEPROM. From the currently stored counter

value there is an initial "Single Operation" forward win-

dow of 16 codes. If the difference between a received

synchronization counter and the last stored counter is

within 16, the intended function will be executed on the

single button press and the new synchronization coun-

ter will be stored. Storing the new synchronization

counter value effectively rotates the entire synchroniza-

tion window.

A "Double Operation" (resynchronization) window fur-

ther exists from the Single Operation window up to 32K

codes forward of the currently stored counter value. It

is referred to as "Double Operation" because a trans-

mission with synchronization counter value in this win-

dow will require an additional, sequential counter

transmission prior to executing the intended function.

Upon receiving the sequential transmission the

decoder executes the intended function and stores the

synchronization counter value. This resynchronization

occurs transparently to the user as it is human nature

to press the button a second time if the first was unsuc-

cessful.

The third window is a "Blocked Window" ranging from

the double operation window to the currently stored

synchronization counter value. Any transmission with

synchronization counter value within this window will

be ignored. This window excludes previously used,

perhaps code-grabbed transmissions from accessing

the system.

FIGURE 3-3: SYNCHRONIZATION WINDOW

Blocked

Entire Window

rotates to eliminate

use of previously

used codes

Single Operation

Window

(32K Codes)

(16 Codes)

Double Operation

(resynchronization)

Window

(32K Codes)

Stored

Synchronization

Counter Value

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HCS500

4.0 INTERFACING TO A

MICROCONTROLLER

The HCS500 interfaces to a microcontroller via a syn-

chronous serial interface. A clock and data line are

used to communicate with the HCS500. The microcon-

troller controls the clock line. There are two groups of

data transfer messages. The first is from the decoder

whenever the decoder receives a valid transmission.

The decoder signals reception of a valid code by taking

the data line high (maximum of 500 ms) The microcon-

troller then services the request by clocking out a data

string from the decoder. The data string contains the

function code, the status bit, and block indicators. The

second is from the controlling microcontroller to the

decoder in the form of a defined command set.

Figure 4-1 shows the HCS500 decoder and the I/O

interface lines necessary to interface to a microcon-

troller.

4.1 Valid Transmission Message

The decoder informs the microcontroller of a valid

transmission by taking the data line high for up to

500 ms. The controlling microcontroller must acknowl-

edge by taking the clock line high. The decoder then

takes the data line low. The microcontroller can then

begin clocking a data stream out of the HCS500. The

data stream consists of:

• START bit ‘0’.

• 2 status bits [REPEAT, VLOW].

• 4-bit function code [S3 S2 S1 S0].

• STOP bit ‘1’.

• 4 bits indicating which block was used

[TX3…TX0].

• 4 bits indicating the number of transmitters

learned into the decoder [CNT3…CNT0].

• 64 bits of the received transmission with the hop-

ping code decrypted.

The decoder will terminate the transmission of the data

stream at any point where the clock is kept low for lon-

ger than 1 ms. Therefore, the microcontroller can only

clock out the required bits. A maximum of 80 bits can

be clocked out of the decoder.

FIGURE 4-1: HCS500 DECODER AND I/O INTERFACE LINES

FIGURE 4-2: DECODER VALID TRANSMISSION MESSAGE

Note: Data is always clocked in/out Least

Significant Bit (LSB) first.

Vss

24LC02

Vcc

SCL

VDD

EE_CLK

EE_DAT

MCLR

Vss

RFIN

S_CLK

S_DAT

VDD

RF RECEIVER

SYNC CLOCK

SYNC DATA

MICRO RESET

HCS500

Decoder Signal Valid

TCLKH

TDS

AB Cii

TPP3

TDHI

TCLA

Received String

S_DAT

TX0 TX3 RX63REPT VLOW S0 S1 S2 S3 CNT0 CNT30 RX0 RX1 RX621

S_CLK

Information

TPP1

TCLKH

TCLKL

Transmission

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