Online Evolution for a High-Speed Image Recognition System Implemented On
a Virtex-II Pro FPGA
Kyrre Glette and Jim Torresen
University of Oslo
Department of Informatics
P.O. Box 1080 Blindern, 0316 Oslo, Norway
{kyrrehg,jimtoer}@ifi.uio.no
Moritoshi Yasunaga
University of Tsukuba
Graduate School of Systems
and Information Engineering
1-1-1 Ten-ou-dai, Tsukuba, Ibaraki, Japan
yasunaga@cs.tsukuba.ac.jp
Abstract
Online incremental evolution for a complex high-speed
pattern recognition architecture has been implemented on
a Xilinx Virtex-II Pro FPGA. The fitness evaluation module
is entirely hardware-based in order to increase the speed of
the circuit evaluation which uses a large training set (360
images/23040 bytes). The fitness evaluation time for 1000
generations consisting of 16 individuals is 623ms, twice as
fast as software fitness evaluation performed on a work-
station running at a 30 times higher clock frequency. The
rest of the genetic algorithm (GA) runs in software on a
PowerPC 405 processor core on the FPGA. The total evo-
lution time for 1000 generations is 1313ms, equivalent to
the total time used by the workstation. Resource utilization
for the fitness evaluation module is 1393 slices (10%) of a
XC2VP30 device.
1 Introduction
Hardware implementation could be important for image
recognition systems requiring a low recognition latency or
high throughput. Furthermore, if the systems are applied in
time-varying environments, and thus need adaptability, on-
line evolvable hardware (EHW) would seem to be a promis-
ing approach [10].
One approach to online reconfigurability is the virtual
reconfigurable circuit (VRC) method proposed by Sekanina
in [7]. This method does not change the bitstream to the
FPGA itself, rather it changes the register values of a circuit
already implemented on the FPGA, and obtains virtual re-
configurability. This approach has a speed advantage over
reconfiguring the FPGA itself, and it is also more feasible
because of proprietary formats preventing direct FPGA bit-
stream manipulation. However, the method requires much
logic resources.
Experiments on image recognition by EHW were first
reported by Iwata et al in [5]. A field programmable logic
array (FPLA) device was utilized for recognition of three
different patterns from black and white input images of 8x8
pixels. An EHW road image recognition system has been
proposed in [8]. A gate array structure was used for cate-
gorizing black and white input images with a resolution of
8x4 pixels. Incremental evolution was applied in order to
increase the evolvability.
A speed limit sign recognition system has been proposed
in [9]. The architecture employed a column of AND gates
followed by a column of OR gates, and then a selector
unit. A maximum detector then made it possible to de-
cide a speed limit from 6 categories. Incremental evolution
was applied in two ways: each subsystem was first evolved
separately, and then in a second step the subsystems were
assembled and the selector units were evolved. The input
images were black and white and had a resolution of 7x5
pixels.
An EHW face image classifier system, logic design us-
ing evolved truth tables (LoDETT), has been presented by
Yasunaga et al. [13]. This system is capable of classifying
large input vectors into several categories. For a face im-
age recognition task, the input images had a resolution of
8x8 pixels of 8-bit gray scale values, belonging to 40 dif-
ferent categories. In this architecture, the classifier function
is directly coded in large AND gates. The classification is
based on detecting the category with the highest number of
activated AND gates. Incremental evolution is utilized for
this system too, where each module for detecting a category
is evolved separately. The average recognition accuracy is
94.7% However, evolution is performed offline and the final
system is synthesized. This approach gives rapid classifica-
tion in a compact circuit, but lacks run-time reconfigurabil-
ity.
Second NASA/ESA Conference on Adaptive Hardware and Systems(AHS 2007)
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