ARM Cortex-A8技术参考手册

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“ARM Cortex-A8 手册，英文版，由 ARM Limited 出版，涵盖技术参考内容，适用于开发应用。” ARM Cortex-A8 是一款基于 ARM 架构的高性能处理器内核，广泛应用于智能手机、嵌入式设备和服务器等场景。该技术参考手册是开发者理解和优化基于 Cortex-A8 内核的应用程序的关键资源。手册中的主要内容可能包括以下几个方面： 1. **体系结构**：Cortex-A8 采用 ARMv7 架构，支持Thumb-2 指令集，提供高性能的32位处理能力。它还包括NEON媒体和浮点处理单元，增强了多媒体和计算密集型任务的性能。 2. **处理器特性**：Cortex-A8 可能包含多级缓存系统，如L1 和 L2 缓存，用于提高内存访问速度。此外，它可能支持乱序执行（Out-of-Order Execution）和动态电压频率调整（DVFS），以实现能效和性能之间的平衡。 3. **虚拟化支持**：Cortex-A8 支持硬件虚拟化技术，允许在一个物理系统上运行多个操作系统实例，这对于云计算和安全应用非常有用。 4. **中断和异常处理**：手册会详细解释处理器如何处理中断和异常，以及相应的处理流程，这对于实时系统和故障诊断至关重要。 5. **调试工具和接口**：Cortex-A8 提供了多种调试接口，如JTAG和SWD，以便开发者可以使用调试器进行代码调试和性能分析。 6. **电源管理**：手册会详细阐述如何利用 ARM 的低功耗技术来优化电源效率，这对于移动设备尤其重要。 7. **性能监控**：可能包含关于性能监测计数器（PMC）的信息，这些计数器可以帮助开发者识别和优化代码性能瓶颈。 8. **编程模型**：手册会提供关于如何编写针对 Cortex-A8 优化的软件的指导，包括并行编程、内存对齐和预编译优化等。 9. **系统集成**：Cortex-A8 通常作为SoC（System-on-Chip）的一部分，手册会讨论如何与其他组件（如GPU、内存控制器和外设接口）协同工作。 10. **错误处理和安全性**：包括错误检测机制，如ECC（Error Correction Code）和故障恢复策略，以及安全特性，如TrustZone技术，用于保护敏感数据和应用。由于手册是技术参考性质，它还会详细描述每个功能的寄存器配置、操作模式、状态寄存器以及具体的指令集说明。开发者可以利用这些信息来编写高效、优化的代码，同时理解处理器在不同工作模式下的行为。不过，要注意的是，手册中的信息可能随着产品更新而变化，因此开发者应使用与目标硬件版本匹配的最新文档。

List of Tables

Table 11-16 GNG[10:0] field ..................................................................................................... 11-13

Table 11-17 L2 cache way grouping ......................................................................................... 11-16

Table 11-18 Identifying failing L2 bits with failing_bits[32:0] ..................................................... 11-17

Table 11-19 Summary of MBIST patterns ................................................................................ 11-24

Table 12-1 Access to CP14 debug registers ............................................................................ 12-7

Table 12-2 CP14 debug registers summary ............................................................................. 12-8

Table 12-3 Debug memory-mapped registers .......................................................................... 12-9

Table 12-4 Processor reset effect on debug and ETM logic ................................................... 12-12

Table 12-5 APB port access with relation to software lock ..................................................... 12-14

Table 12-6 Debug registers access with relation to power-down event .................................. 12-15

Table 12-7 Power management registers access with relation to power-down event ............ 12-16

Table 12-8 ETM and CTI registers access with relation to power-down event ....................... 12-16

Table 12-9 Terms used in register descriptions ...................................................................... 12-18

Table 12-10 CP14 debug registers ........................................................................................... 12-18

Table 12-11 Debug ID Register bit functions ............................................................................ 12-20

Table 12-12 Debug ROM Address Register bit functions ......................................................... 12-22

Table 12-13 Debug Self Address Offset Register bit functions ................................................. 12-23

Table 12-14 Debug Status and Control Register bit functions .................................................. 12-25

Table 12-15 Data Transfer Register bit functions ..................................................................... 12-32

Table 12-16 Watchpoint Fault Address Register bit functions .................................................. 12-33

Table 12-17 Vector Catch Register bit functions ...................................................................... 12-34

Table 12-18 Event Catch Register bit functions ........................................................................ 12-36

Table 12-19 Debug State Cache Control Register bit functions ............................................... 12-37

Table 12-20 Instruction Transfer Register bit functions ............................................................ 12-38

Table 12-21 Debug Run Control Register bit functions ............................................................ 12-39

Table 12-22 Breakpoint Value Registers bit functions .............................................................. 12-40

Table 12-23 Breakpoint Control Registers bit functions ............................................................ 12-41

Table 12-24 Meaning of BVR bits [22:20] ................................................................................. 12-43

Table 12-25 Watchpoint Value Registers bit functions ............................................................. 12-44

Table 12-26 Watchpoint Control Registers bit functions ........................................................... 12-46

Table 12-27 OS Lock Access Register bit functions ................................................................. 12-49

Table 12-28 OS Lock Status Register bit functions .................................................................. 12-50

Table 12-29 OS Save and Restore Register bit functions ........................................................ 12-51

Table 12-30 PRCR bit functions ............................................................................................... 12-53

Table 12-31 PRSR bit functions ................................................................................................ 12-54

Table 12-32 Management registers .......................................................................................... 12-56

Table 12-33 Processor Identifier Registers ............................................................................... 12-57

Table 12-34 Integration Internal Output Control Register bit functions ..................................... 12-59

Table 12-35 Integration External Output Control Register bit functions .................................... 12-61

Table 12-36 Integration Input Status Register bit functions ...................................................... 12-62

Table 12-37 Integration Mode Control Register bit functions .................................................... 12-63

Table 12-38 Claim Tag Set Register bit functions .................................................................... 12-64

Table 12-39 Claim Tag Clear Register bit functions ................................................................. 12-64

Table 12-40 Lock Access Register bit functions ....................................................................... 12-65

Table 12-41 Lock Status Register bit functions ........................................................................ 12-66

Table 12-42 Authentication Status Register bit functions ......................................................... 12-67

Table 12-43 Device Type Register bit functions ....................................................................... 12-68

List of Tables

Table 12-44 Peripheral Identification Registers ........................................................................ 12-68

Table 12-45 Fields in the Peripheral Identification Registers .................................................... 12-69

Table 12-46 Peripheral ID Register 0 bit functions .................................................................... 12-70

Table 12-47 Peripheral ID Register 1 bit functions .................................................................... 12-70

Table 12-48 Peripheral ID Register 2 bit functions .................................................................... 12-70

Table 12-49 Peripheral ID Register 3 bit functions .................................................................... 12-71

Table 12-50 Peripheral ID Register 4 bit functions .................................................................... 12-71

Table 12-51 Component Identification Registers ...................................................................... 12-71

Table 12-52 Processor behavior on debug events .................................................................... 12-74

Table 12-53 Values in Link Register after exceptions ............................................................... 12-77

Table 12-54 Read PC value after debug state entry ................................................................. 12-81

Table 12-55 Permitted updates to the CPSR in debug state .................................................... 12-84

Table 12-56 Accesses to CP15 and CP14 registers in debug state ......................................... 12-85

Table 12-57 Authentication signal restrictions ........................................................................... 12-95

Table 12-58 Values to write to BCR for a simple breakpoint ................................................... 12-102

Table 12-59 Values to write to WCR for a simple watchpoint ................................................. 12-104

Table 12-60 Example byte address masks for watchpointed objects ..................................... 12-105

Table 13-1 Single-precision three-operand register usage ..................................................... 13-10

Table 13-2 Single-precision two-operand register usage ........................................................ 13-10

Table 13-3 Double-precision three-operand register usage .................................................... 13-10

Table 13-4 Double-precision two-operand register usage ...................................................... 13-11

Table 13-5 NEON and VFPLite system registers .................................................................... 13-12

Table 13-6 Accessing NEON and VFPLite system registers ................................................... 13-12

Table 13-7 FPSID Register bit functions ................................................................................. 13-14

Table 13-8 FPSCR Register bit functions ............................................................................... 13-15

Table 13-9 Vector length and stride combinations .................................................................. 13-17

Table 13-10 Floating-Point Exception Register bit functions ..................................................... 13-18

Table 13-11 MVFR0 Register bit functions ............................................................................... 13-19

Table 13-12 MVFR1 Register bit functions ............................................................................... 13-20

Table 13-13 Default NaN values ............................................................................................... 13

-23

Table 13-14 QNaN and SNaN handling .................................................................................... 13-24

Table 14-1 ETM configuration ................................................................................................... 14-7

Table 14-2 ETM register summary ............................................................................................ 14-9

Table 14-3 ID Register bit functions ........................................................................................ 14-12

Table 14-4 Configuration Code Register bit functions ............................................................. 14-13

Table 14-5 Configuration Code Extension Register bit functions ............................................ 14-14

Table 14-6 Peripheral Identification Registers bit functions .................................................... 14-15

Table 14-7 Component Identification Registers bit functions .................................................. 14-17

Table 14-8 Output signals that can be controlled by the Integration Test Registers ............... 14-18

Table 14-9 Input signals that can be read by the Integration Test Registers .......................... 14-18

Table 14-10 ITMISCOUT Register bit functions ........................................................................ 14-19

Table 14-11 ITMISCIN Register bit functions ............................................................................ 14-20

Table 14-12 ITTRIGGER Register bit functions ........................................................................ 14-20

Table 14-13 ITATBDATA0 Register bit functions ...................................................................... 14-21

Table 14-14 ITATBCTR2 Register bit functions ........................................................................ 14-22

Table 14-15 ITATBCTR1 Register bit functions ........................................................................ 14-22

Table 14-16 ITATBCTR0 Register bit functions ........................................................................ 14-23

List of Tables

Table 14-17 PMU event number mappings .............................................................................. 14-33

Table 14-18 PMU event cycle mappings .................................................................................. 14-35

Table 15-1 Trigger inputs .......................................................................................................... 15-6

Table 15-2 Trigger outputs ........................................................................................................ 15-6

Table 15-3 CTI register summary ........................................................................................... 15-10

Table 15-4 CTI Control Register bit functions ......................................................................... 15-13

Table 15-5 CTI Interrupt Acknowledge Register bit functions ................................................. 15-14

Table 15-6 CTI Application Trigger Set Register bit functions ................................................ 15-14

Table 15-7 CTI Application Trigger Clear Register bit functions ............................................. 15-15

Table 15-8 CTI Application Pulse Register bit functions ......................................................... 15-16

Table 15-9 CTI Trigger to Channel Enable Registers bit functions ......................................... 15-17

Table 15-10 CTI Channel to Trigger Enable Registers bit functions ......................................... 15-18

Table 15-11 CTI Trigger In Status Register bit functions .......................................................... 15-18

Table 15-12 CTI Trigger Out Status Register bit functions ....................................................... 15-19

Table 15-13 CTI Channel In Status Register bit functions ........................................................ 15-20

Table 15-14 CTI Channel Gate Register bit functions .............................................................. 15-20

Table 15-15 ASIC Control Register bit functions ...................................................................... 15-22

Table 15-16 CTI Channel Out Status Register bit functions ..................................................... 15-23

Table 15-17 CTI Integration Test Registers .............................................................................. 15-24

Table 15-18 ITTRIGINACK Register bit functions .................................................................... 15-25

Table 15-19 ITCHOUT Register bit functions ........................................................................... 15-25

Table 15-20 ITTRIGOUT Register bit functions ........................................................................ 15-26

Table 15-21 ITTRIGOUT connections to other integration test registers .................................. 15-26

Table 15-22 ITTRIGOUTACK Register bit functions ................................................................ 15-27

Table 15-23 ITTRIGOUTACK connections to other integration test registers .......................... 15-27

Table 15-24 ITCHIN Register bit functions ............................................................................... 15-28

Table 15-25 ITTRIGIN Register bit functions ............................................................................ 15-28

Table 15-26 ITTRIGIN connections to other integration test registers ...................................... 15-29

Table 15-27 Authentication Status Register bit functions ......................................................... 15-30

Table 15-28 Device ID Register bit functions ............................................................................ 15-30

Table 15-29 Device Type Identifier Register bit functions ........................................................ 15-31

Table 15-30 Peripheral Identification Registers bit functions .................................................... 15-31

Table 15-31 Component Identification Registers bit functions .................................................. 15-33

Table 16-1 Data-processing instructions with a destination ...................................................... 16-6

Table 16-2 Data-processing instructions without a destination ................................................. 16-6

Table 16-3 MOV and MOVN instructions .................................................................................. 16-7

Table 16-4 Multiply instructions ................................................................................................ 16-8

Table 16-5 Parallel arithmetic instructions ................................................................................ 16-9

Table 16-6 Extended instructions ............................................................................................. 16-9

Table 16-7 Miscellaneous data-processing instructions ........................................................... 16-9

Table 16-8 Status register access instructions ....................................................................... 16-10

Table 16-9 Load instructions ................................................................................................... 16-11

Table 16-10 Store instructions ..................................................................................................

16-11

Table 16-11 Branch instructions ............................................................................................... 16-13

Table 16-12 Dual-issue restrictions .......................................................................................... 16-14

Table 16-13 Memory system effects on instruction timings ...................................................... 16-15

Table 16-14 Thumb-2EE instructions ....................................................................................... 16-17

List of Tables

Table 16-15 NEON integer ALU instructions ............................................................................. 16-22

Table 16-16 NEON integer multiply instructions ....................................................................... 16-26

Table 16-17 NEON integer shift instructions ............................................................................. 16-29

Table 16-18 NEON floating-point instructions ........................................................................... 16-30

Table 16-19 NEON byte permute instructions ........................................................................... 16-32

Table 16-20 NEON load/store instructions ................................................................................ 16-35

Table 16-21 NEON register transfer instructions ...................................................................... 16-42

Table 16-22 VFPLite Instruction cycle counts ........................................................................... 16-43

Table 17-1 Format of timing parameter tables .......................................................................... 17-3

Table 17-2 Timing parameters of AXI interface ......................................................................... 17-4

Table 17-3 Timing parameters of ETM ATB and CTI interfaces ............................................... 17-6

Table 17-4 Timing parameters of debug ATB interface ............................................................ 17-7

Table 17-5 Timing parameters of the L1 and L2 MBIST interface ............................................ 17-9

Table 17-6 Timing parameters of the L2 preload interface ..................................................... 17-10

Table 17-7 Timing parameters of the DFT interface ............................................................... 17-11

Table 17-8 Timing parameters of miscellaneous signals ........................................................ 17-12

Table A-1 AXI interface .............................................................................................................. A-2

Table A-2 ETM ATB interface .................................................................................................... A-3

Table A-3 MBIST interface ........................................................................................................ A-4

Table A-4 DFT and additional MBIST pin requirements ............................................................ A-5

Table A-5 Preload engine interface ........................................................................................... A-7

Table A-6 Debug APB interface ................................................................................................. A-8

Table A-7 Miscellaneous signals ............................................................................................. A-10

Table A-8 Miscellaneous debug signals .................................................................................. A-13

Table A-9 Miscellaneous ETM and CTI signals ....................................................................... A-15

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