TMS320VC5402 DSP详细规格与功能概述

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本文档是关于TMS320VC5402 DSP (数字信号处理器) 的详细说明书，它提供了这款器件的关键特性和技术规格。该芯片属于TI (德州仪器) 的产品系列，其设计旨在支持高级多总线架构，具有独特的功能集。首先，TMS320VC5402拥有三个独立的16位数据内存总线和一个程序内存总线，这使得数据和程序的传输能够高效地在不同的存储器之间进行。这为处理复杂的实时应用提供了灵活性。该芯片的核心组成部分包括一个强大的40位算术逻辑单元(Alu)，具备40位桶移位器和两个独立的40位累加器，支持高效的并行计算和算术操作。特别是，它配备了一个17x17位的并行乘法器，与一个40位专用加法器相结合，实现了非流水线的单周期乘法/累加(MAC)运算，这对于需要高精度和速度的应用非常重要。 CSSU (Compare, Select, and Store Unit) 是Viterbi算法选择器的重要组成部分，用于实现精确的加法/比较操作，进一步提升了处理性能。此外，40位累加器还支持单周期指数编码，能够在单个时钟周期内计算出累加器值的指数部分。芯片内部有两个地址生成器，每个带有八个辅助寄存器和两个辅助寄存器算术单元(ARAUs)，这增加了地址操作的灵活性和扩展性。数据总线设计还包括了bus-holder功能，允许在数据传输过程中保持某些数据，提高了数据处理的连续性和效率。 TMS320VC5402还支持扩展地址模式，能够访问最大1M×16位的外部程序空间，这扩大了它的应用范围。内置的存储器包括4Kx16位的片上只读存储器(ROM) 和16Kx16位的双访问片上随机存取存储器(RAM)，满足不同类型的存储需求。在指令集方面，芯片提供了单指令重复(SIR) 和块重复操作，便于对程序代码进行优化，同时，还有块内存移动指令，能有效提升程序和数据的处理效率。这些特性使得TMS320VC5402成为工业控制、通信系统、信号处理和多媒体应用的理想选择，尤其是那些需要高性能、低延迟以及高度集成的系统设计者会非常看重这款器件。 TMS320VC5402是一款功能强大的DSP，它凭借其多总线架构、高级算术能力、高效的存储器管理和灵活的指令集，为现代电子设计提供了强大的计算平台。深入理解并利用这些特性和优势，能够显著提高系统的整体性能和开发效率。

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SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

memory

The 5402 device provides both on-chip ROM and RAM memories to aid in system performance and integration.

on-chip ROM with bootloader

The 5402 features a 4K-word

× 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the

5402 programmed with contents unique to any particular application. A security option is available to protect

a custom ROM. This security option is described in the TMS320C54x DSP CPU and Peripherals Reference Set,

Volume 1 (literature number SPRU131). Note that only the ROM security option, and not the ROM/RAM option,

is available on the 5402 .

A bootloader is available in the standard 5402 on-chip ROM. This bootloader can be used to automatically

transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC

is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location

contains a branch instruction to the start of the bootloader program. The standard 5402 bootloader provides

different ways to download the code to accomodate various system requirements:

D Parallel from 8-bit or 16-bit-wide EPROM

D Parallel from I/O space 8-bit or 16-bit mode

D Serial boot from serial ports 8-bit or 16-bit mode

D Host-port interface boot

The standard on-chip ROM layout is shown in Table 1.

Table 1. Standard On-Chip ROM Layout

†

ADDRESS RANGE DESCRIPTION

F000h − F7FFh Reserved

F800h − FBFFh Bootloader

FC00h − FCFFh µ-law expansion table

FD00h − FDFFh A-law expansion table

FE00h − FEFFh Sine look-up table

FF00h − FF7Fh Reserved

FF80h − FFFFh Interrupt vector table

†

In the ’VC5402 ROM, 128 words are reserved for factory device-testing purposes. Application

code to be implemented in on-chip ROM must reserve these 128 words at addresses

FF00h–FF7Fh in program space.

on-chip RAM

The 5402 device contains 16K

× 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed of two

blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write

in one cycle. The DARAM is located in the address range 0060h−3FFFh in data space, and can be mapped

into program/data space by setting the OVLY bit to one.



   

SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

memory map

Page 0 Program

Hex

Data

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

MP/MC

= 0

(Microcomputer Mode)

MP/MC= 1

(Microprocessor Mode)

0000

007F

0080

FFFF

Reserved

(OVLY = 1)

External

(OVLY = 0)

Interrupts

(External)

FF80

Memory

Mapped

Registers

On-Chip DARAM

(16K x 16-bit)

ROM (DROM=1)

or External

(DROM=0)

0080

FFFF

Hex

0000

FF7F

FF00

FEFF

EFFF

F000

FFFF

3FFF

4000

0060

007F

0000

Hex

Page 0 Program

External

Scratch-Pad

RAM

Reserved

(DROM=1)

or External

(DROM=0)

005F

Reserved

(OVLY = 1)

External

(OVLY = 0)

007F

0080

3FFF

4000

On-Chip DARAM

(OVLY = 1)

External

(OVLY = 0)

FF00

FEFF

EFFF

F000

External

On-Chip ROM

(4K x 16-bit)

Interrupts

(On-Chip)

3FFF

4000

Reserved

FF7F

FF80

Figure 1. Memory Map

relocatable interrupt vector table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that

the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the

code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch

instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate

interrupt service routine with minimal overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,

these vectors can be remapped to the beginning of any 128-word page in program space after device reset.

This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see Figure 2) with the

appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped

to the new 128-word page.

NOTE: The hardware reset (RS

) vector cannot be remapped because a hardware reset loads the IPTR

with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

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