5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HSYNC_R
VSYNC_R
LVDSB1+
LVDSB1-
LVDSBC+
LVDSBC-
LVDSA0+
LVDSA0-
LVDSAC-
LVDSAC+
LVDSA2-
LVDSA2+
LVDSB2+
LVDSB2-
LVDSA1-
LVDSA1+
LVDSB0+
LVDSB0-
TV_COMPS
TV_LUMA
TV_CRMA
CRT_R
CRT_G
CRT_B
CRT_G
CRT_B
CRT_R
CRT_VSYNC
CRT_HSYNC
3VDDCDA
3VDDCCL
GMCH_LVDDEN
GMCH_ENBKL
EDID_DAT_LCD
EDID_CLK_LCD
PEG_RXN13
PEG_RXN14
PEG_RXN0
PEG_RXN1
PEG_RXN3
PEG_RXN4
PEG_RXN6
PEG_RXP2
PEG_RXP3
PEG_RXP5
PEG_RXP6
PEG_RXP8
PEG_RXP9
PEG_RXP11
PEG_RXP12
PEG_RXP14
PEG_RXP15
PEG_RXN9
PEG_RXN12
PEG_RXN15
PEG_RXN2
PEG_RXN5
PEG_RXP0
PEG_RXP1
PEG_RXP4
PEG_RXP7
PEG_RXP10
PEG_RXP13
PEGCOMP
PEG_RXN7
PEG_RXN8
PEG_RXN10
PEG_RXN11
PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_M_TXP5
PEG_M_TXP4
PEG_M_TXP3
PEG_M_TXP10
PEG_M_TXP6
PEG_M_TXP2
PEG_M_TXP7
PEG_M_TXP12
PEG_M_TXP9
PEG_M_TXP11
PEG_M_TXP8
PEG_M_TXP14
PEG_M_TXP1
PEG_M_TXP15
PEG_M_TXP0
PEG_M_TXP13
PEG_M_TXN4
PEG_M_TXN3
PEG_M_TXN6
PEG_M_TXN9
PEG_M_TXN10
PEG_M_TXN7
PEG_M_TXN12
PEG_M_TXN14
PEG_M_TXN15
PEG_M_TXN1
PEG_M_TXN0
PEG_TXN5
PEG_TXN11
PEG_M_TXN5
PEG_M_TXN2
PEG_M_TXN8
PEG_M_TXN13
PEG_M_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN10
PEG_TXN14
PEG_TXN4
PEG_TXN6
PEG_TXN1
PEG_TXN0
PEG_TXN15
PEG_TXN7
PEG_TXN8
PEG_TXN2
PEG_TXN3
PEG_TXN9
TV_LUMA
TV_CRMA
TV_COMPS
EDID_CLK_LCD
EDID_DAT_LCD
LVDSB1+37
LVDSB1-37
LVDSA0+37
LVDSA0-37
LVDSAC+37
LVDSAC-37
LVDSA2-37
LVDSA2+37
LVDSB2-37
LVDSB2+37
LVDSA1-37
LVDSA1+37
LVDSB0-37
LVDSB0+37
LVDSBC-37
LVDSBC+37
TV_COMPS17
TV_LUMA17
TV_CRMA17
CRT_R17
CRT_G17
CRT_B17
CRT_HSYNC17
CRT_VSYNC17
3VDDCDA17
3VDDCCL17
GMCH_ENBKL16
GMCH_LVDDEN16
PEG_RXP[0..15] 18
PEG_RXN[0..15] 18
PEG_M_TXP[0..15] 18
PEG_M_TXN[0..15] 18
CFG137
CFG77
CFG87
CFG57
CFG167
CFG197
CFG97
CFG207
CFG127
EDID_CLK_LCD37
EDID_DAT_LCD37
+3VS
+3VS
+3VS
+3VS
+VCC_PEG
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
IGT30 LA-3571P
0.1
CRESTLINE((3/6)-VGA/LVDS/TV
Custom
947Monday, December 25, 2006
2006/08/04 2006/10/06
Compal Electronics, Inc.
For Calero: 255ohm
For Crestline:1.3kohm
For Calero: 1.5Kohm
For Crestline:2.4kohm
PEGCOMP trace width
and spacing is 20/25 mils.
CFG9
CFG[17:3] have internal pull up
CFG[19:18] have internal pull down
Strap Pin Table
CFG[15:14] Reserved
Reserved
Reserved
CFG[2:0] FSB Freq select
(PCIE Graphics Lane Reversal)
1 = Low Power mode
0 = Normal mode
0 = Reverse Lane
1 = Reverse Lane
*
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved
(Lane number in Order)
CFG[18:17] Reserved
SDVO_CTRLDATA
1 = PCIE/SDVO are operating simu.
*
*
*
*
00 = Reserved
0 = DMI x 2
*
0 = Disabled
*
(Default)
0 = No SDVO Device Present
0 = Normal Operation
1 = SDVO Device Present
1 = Enabled
CFG8 (Low power PCIE)
CFG[13:12] (XOR/ALLZ)
CFG[11:10]
CFG20 (PCIE/SDVO concurrent)
CFG7 (CPU Strap)
CFG6
CFG16 (FSB Dynamic ODT)
CFG19 (DMI Lane Reversal)
CFG5 (DMI select)
1 = Mobile CPU
0 = Reserved
1 = DMI x 4
1 = Normal Operation
*
0 = Only PCIE or SDVO is operational.
*
R62 2.4K_0402_1%
12
R59
2.2K_0402_5%
UMA@
12
R66
24.9_0402_1%
1 2
C243 0.1U_0402_16V4ZVGA@
R27 4.02K_0402_1%@
1 2
C279 0.1U_0402_16V4ZVGA@
C223 0.1U_0402_16V4ZVGA@
C239 0.1U_0402_16V4ZVGA@
R415 150_0603_1%UMA@
12
C258 0.1U_0402_16V4ZVGA@
R429 10K_0402_5%
1 2
C264 0.1U_0402_16V4ZVGA@
C242 0.1U_0402_16V4ZVGA@
R413 4.02K_0402_1%@
1 2
C233 0.1U_0402_16V4ZVGA@
R32 4.02K_0402_1%@
1 2
R419 150_0603_1%UMA@
12
R33 4.02K_0402_1%@
1 2
R422 39_0402_1%
1 2
C261 0.1U_0402_16V4ZVGA@
C282 0.1U_0402_16V4ZVGA@
C218 0.1U_0402_16V4ZVGA@
R25 4.02K_0402_1%@
1 2
C221 0.1U_0402_16V4ZVGA@
C257 0.1U_0402_16V4ZVGA@
R424 39_0402_1%
1 2
C256 0.1U_0402_16V4ZVGA@
C278 0.1U_0402_16V4ZVGA@
C263 0.1U_0402_16V4ZVGA@
C235 0.1U_0402_16V4ZVGA@
C262 0.1U_0402_16V4ZVGA@
R414 150_0603_1%UMA@
12
C284 0.1U_0402_16V4ZVGA@
R425 10K_0402_5%
1 2
R55 4.02K_0402_1%@
1 2
C222 0.1U_0402_16V4ZVGA@
C241 0.1U_0402_16V4ZVGA@
C234 0.1U_0402_16V4ZVGA@
C224 0.1U_0402_16V4ZVGA@
R29 4.02K_0402_1%@
1 2
C217 0.1U_0402_16V4ZVGA@
C236 0.1U_0402_16V4ZVGA@
C276 0.1U_0402_16V4ZVGA@
C259 0.1U_0402_16V4ZVGA@
R421 150_0603_1%UMA@
12
C283 0.1U_0402_16V4ZVGA@
C277 0.1U_0402_16V4ZVGA@
R26 4.02K_0402_1%@
1 2
C281 0.1U_0402_16V4ZVGA@
R418 150_0603_1%UMA@
12
R52 2.2K_0402_5%
1 2
LVDS
PCI-EXPRESS GRAPHICS
TV VGA
U22C
CRESTLINE_1p0
PEG_COMPI
N43
PEG_COMPO
M43
PEG_RX#_0
J51
PEG_RX#_1
L51
PEG_RX#_2
N47
PEG_RX#_3
T45
PEG_RX#_4
T50
PEG_RX#_5
U40
PEG_RX#_6
Y44
PEG_RX#_7
Y40
PEG_RX#_8
AB51
PEG_RX#_9
W49
PEG_RX#_10
AD44
PEG_RX#_11
AD40
PEG_RX#_12
AG46
PEG_RX#_13
AH49
PEG_RX#_14
AG45
PEG_RX#_15
AG41
PEG_RX_0
J50
PEG_RX_1
L50
PEG_RX_2
M47
PEG_RX_3
U44
PEG_RX_4
T49
PEG_RX_5
T41
PEG_RX_6
W45
PEG_RX_7
W41
PEG_RX_8
AB50
PEG_RX_9
Y48
PEG_RX_10
AC45
PEG_RX_11
AC41
PEG_RX_12
AH47
PEG_RX_13
AG49
PEG_RX_14
AH45
PEG_RX_15
AG42
PEG_TX#_0
N45
PEG_TX#_10
AC46
PEG_TX#_3
N51
PEG_TX#_4
R50
PEG_TX#_5
T42
PEG_TX#_6
Y43
PEG_TX#_7
W46
PEG_TX#_8
W38
PEG_TX#_9
AD39
PEG_TX#_1
U39
PEG_TX#_11
AC49
PEG_TX#_12
AC42
PEG_TX#_13
AH39
PEG_TX#_14
AE49
PEG_TX#_15
AH44
PEG_TX#_2
U47
PEG_TX_0
M45
PEG_TX_1
T38
PEG_TX_2
T46
PEG_TX_3
N50
PEG_TX_4
R51
PEG_TX_5
U43
PEG_TX_6
W42
PEG_TX_7
Y47
PEG_TX_8
Y39
PEG_TX_9
AC38
PEG_TX_10
AD47
PEG_TX_11
AC50
PEG_TX_12
AD43
PEG_TX_13
AG39
PEG_TX_14
AE50
PEG_TX_15
AH43
L_CTRL_CLK
E39
L_CTRL_DATA
E40
L_DDC_CLK
C37
L_DDC_DATA
D35
L_VDD_EN
K40
LVDS_IBG
L41
LVDS_VBG
L43
LVDS_VREFH
N41
LVDS_VREFL
N40
LVDSA_CLK#
D46
LVDSA_CLK
C45
LVDSA_DATA#_0
G51
LVDSA_DATA#_1
E51
LVDSA_DATA#_2
F49
LVDSA_DATA_1
E50
LVDSA_DATA_2
F48
LVDSB_CLK#
D44
LVDSB_CLK
E42
LVDSB_DATA#_0
G44
LVDSB_DATA#_1
B47
LVDSB_DATA#_2
B45
LVDSB_DATA_1
A47
LVDSB_DATA_2
A45
L_BKLT_EN
H39
TVA_DAC
E27
TVB_DAC
G27
TVC_DAC
K27
TVA_RTN
F27
TVB_RTN
J27
TVC_RTN
L27
CRT_BLUE
H32
CRT_BLUE#
G32
CRT_DDC_CLK
K33
CRT_DDC_DATA
G35
CRT_GREEN
K29
CRT_GREEN#
J29
CRT_HSYNC
F33
CRT_TVO_IREF
C32
CRT_RED
F29
CRT_RED#
E29
CRT_VSYNC
E33
LVDSA_DATA_0
G50
LVDSB_DATA_0
E44
L_BKLT_CTRL
J40
TV_DCONSEL_0
M35
TV_DCONSEL_1
P33
R56
2.2K_0402_5%
UMA@
12
R416 150_0603_1%UMA@
12
R417
1.3K_0402_1%
12
C225 0.1U_0402_16V4ZVGA@
C219 0.1U_0402_16V4ZVGA@
R58 4.02K_0402_1%@
1 2