9
TUSB546A-DCI
www.ti.com.cn
ZHCSGH4B –JUNE 2017–REVISED MAY 2019
Copyright © 2017–2019, Texas Instruments Incorporated
6.9 Timing Requirements
MIN NOM MAX UNIT
USB Gen 1
t
IDLEEntry
Delay from U0 to electrical idle See Figure 14 10 ns
t
IDELExit_U1
U1 exist time: break in electrical idle to
the transmission of LFPS
See Figure 14 6 ns
t
IDLEExit_U2U3
U2/U3 exit time: break in electrical idle to transmission of LFPS 10 µs
t
RXDET_INTVL
RX detect interval while in Disconnect 12 ms
t
IDLEExit_DISC
Disconnect Exit Time 10 µs
t
Exit_SHTDN
Shutdown Exit Time 1 ms
t
DIFF_DLY
Differential Propagation Delay See Figure 13 300 ps
t
R,
t
F
Output Rise/Fall time (see Figure 15)
20%-80% of differential
voltage measured 1 inch
from the output pin
40 ps
t
RF_MM
Output Rise/Fall time mismatch
20%-80% of differential
voltage measured 1 inch
from the output pin
2.6 ps
6.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUXp or AUXn and SBU1 or SBU2
t
AUX_PD
Switch propagation delay 400 ps
t
AUX_SW_OFF
Switching time CTL1 to switch OFF. Not including
TCTL1_DEBOUNCE.
500 ns
t
AUX_SW_ON
Switching time CTL1 to switch ON 500 ns
t
AUX_INTRA
Intra-pair output skew 100 ps
USB3.1 and DisplayPort mode transition requirement GPIO mode
t
GP_USB_4DP
Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only
mode to 4-Lane DisplayPort mode or vice versa.
4 µs
CTL1 and HPDIN
t
CTL1_DEBOUNCE
CTL1 and HPDIN debounce time when transitioning from H to L. 2 10 ms
I
2
C (Refer to Figure 11)
f
SCL
I
2
C clock frequency 1 MHz
t
BUF
Bus free time between START and STOP conditions 0.5 µs
t
HDSTA
Hold time after repeated START condition. After this period, the first
clock pulse is generated
0.26 µs
t
LOW
Low period of the I
2
C clock 0.5 µs
t
HIGH
High period of the I
2
C clock 0.26 µs
t
SUSTA
Setup time for a repeated START condition 0.26 µs
t
HDDAT
Data hold time 0 μs
t
SUDAT
Data setup time 50 ns
t
R
Rise time of both SDA and SCL signals 120 ns
t
F
Fall time of both SDA and SCL signals
20 × (V
(I2C)
/5.5
V)
120 ns
t
SUSTO
Setup time for STOP condition 0.26 μs
C
b
Capacitive load for each bus line 150 pF
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